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MICRONAS INTERMETALL
CCU 3000, CCU 3000-I, CCU 3001, CCU 3001-I, Central Control Unit
MICRONAS
Edition Feb. 14, 1995 6251-367-1DS
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
Contents Page 4 4 5 5 5 5 5 5 5 5 6 7 7 7 8 8 10 12 14 19 21 21 22 22 22 22 23 23 24 25 28 31 32 32 32 32 33 34 34 36 36 37 38 59 61 62 2 Section 1. 1.1. 2. 2.1. 2.2. 2.3. 2.4. 2.5. 2.6. 2.7. 2.8. 2.8.1. 2.8.2. 2.8.3. 2.9. 2.10. 2.11. 2.12. 2.13. 2.14. 2.15. 2.16. 3. 3.1. 3.2. 3.3. 4. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.3. 4.6.4. 4.6.5. 4.6.6. 4.6.7. 4.6.8. 4.6.9. 4.6.10. 5. 6. 7. Title Introduction Features of the CCU 3000, CCU 3000-I, CCU 3001, CCU 3001-I Functional Description ROM RAM CPU Clock Generator PORT 1 to PORT 3, PORT 6 to PORT 8 PORT 4 I/O-Lines P50 to P55 Special Mode of Port 7 Power-down Control External Memory (Special Mode P77) R/W Output (Special Mode P76) Banking Address (Special Mode P70 to P75) Reset Function Control Register Interrupt Controller IM Bus Interface Multifunctional Timer Watchdog IR-Input Mask Options Definitions Interrupt Definitions Memory Mappings I/O Definitions Specifications Outline Dimensions Pin Configuration Pin Connections and Short Descriptions Pin Descriptions Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Recommended Crystal Characteristics DC Characteristics Using External Devices AC Characteristics IM Bus Waveforms Description of the IM Bus Recommended Operating Conditions of IM Bus Registers Index Addendum: CCU 3000, CCU 3000-I EMU Versions Addendum: CCU 3000 1 m Version MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
Contents, continued Page 62 62 63 63 64 65 66 66 66 66 66 66 67 71 73 74 76 Section 7.1. 7.1.1. 7.1.2. 7.1.3. 7.1.4. 7.1.5. 8. 8.1. 8.2. 8.3. 8.4. 8.5. 8.6. 8.7. 8.7.1. 8.8. 9. Title Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Recommended Crystal Characteristics DC Characteristics AC Characteristics Addendum: CCU 3000-I Specification Changes to CCU3000 Definitions Interrupt Definitions Memory Mappings I/O Definitions I2C and IM Bus Interface Pin Connections and Short Descriptions DC Parameters I2C Bus Master Interface List of Registers that Differ from CCU 3000, CCU 3001 Data Sheet History
MICRONAS INTERMETALL
3
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
1. Introduction The CCU 3000, CCU 3000-I, CCU 3001, CCU 3001-I are integrated circuits designed in 1.2 m CMOS technology, with the exception of CCU 3000, TC18 and TC19, which is designed in 1 m CMOS technology. The CPU contained on the chips is a functionally unchanged 65C02-core, which means that for program development, systems can be used which are on the market; including high level language compilers. The pin numbers mentioned in this data sheet refer to the 68-pin PLCC package unless otherwise designated. The CCU 3000-I is described separately in an addendum on page 66. - 51 I/O lines (CCU 3001) - 26 I/O lines (CCU 3000) - clock generator with programmable clock frequency - 8 level interrupt controller - CCU 3000, CCU 3001: 2 Multimaster IM bus interfaces - CCU 3000-I, CCU 3001-I: 1I2C/IM bus and 1 Multimaster IM bus interface (see addendum) - IR-input for software-decoded IR-systems - on-chip power on, stand-by and clock supervision logic - on-chip watchdog - 3 multifunctional timers 1.1. Features of the CCU 3000, CCU 3000-I, CCU 3001, CCU 3001-I - CCU 3000 = ROM-less version of the CCU 3001 - 65C02 CPU with max. 8 MHz clock - 32 kByte internal ROM (CCU 3001 only) - 1344 internal Bytes RAM with stand-by option - supports memory banking (external 2MBytes) - power down signal for external memory - mask option: EMU mode - programs can be written in Assembler or in "C" - CCU 3000 TC 18/19: 1.0 m CMOS technology, (see addendum) - application software available
6
8
8
5
A0 to A15 (P20 to P37)
16
1 R/W/P40
D0 to D7 (P10 to P17)
8
Fig. 1-1: CCU 3000, CCU 3001 block diagram 4
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P5 P6 P7 P8 Watch- dog 3 CPU IM 1 Power on Logic INTERRUPT CONTROLLER IM 2 3 Stand- by Logic ROM 32 kByte (3001 only) RAM 1344 Bytes 1 IR TIMER1 TIMER2 TIMER3 CLOCK 1 1 1 2 MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
2. Functional Description 2.1. ROM The chip is equipped with 32 kByte mask-programmable ROM. The ROM uses up the address space from 8000H to FFFFH. This ROM can be supplemented or replaced externally. Only the CCU 3001 has an internal ROM. 2.2. RAM The RAM area is split into three parts: - page 0 - page 1 - page 3, 4, 5, 6 (address 0 to FFH) (address 100H to 1FFH) (address 300H to 63FH) 2.6. PORT 4 PORT 4 consists of only one line (LSB, P40). After a reset, PORT 4 operates as an input only. As soon as PORT 4 is written for the first time, it is switched to output mode (push-pull). Later read accesses read the actual level at port 4. If bit 3 in the control word is active, P4 is used as an R/W-line. If the internal CPU is active, R/W is an output line, otherwise it is an input. But P4 has another, very important function during RESET. The level at P4 during RESET decides whether the control word is read from the internal ROM (FFF9H) or from the external memory. It is therefore important that the desired level during RESET is set at P4. An internal pull-down resistor of approx. 100 k is integrated in the CCU 3001, which ensures that the control word is read by the internal ROM. The external control word access is obtained via an external pull-up resistor of approx. 5 k. The CCU 3000 has an internal pull-up resistor at P4 (external ROM access). The further mode of operation of the CCU 3000, CCU 3001 depends only on the control word though. Please note that this mode is always necessary for the CCU 3000 since this device does not have internal ROM! 2.7. I/O-Lines P50 to P55 The 6 additional I/O-lines have a two-fold function: - input or output line (open drain output) or - fully decoded I/O-select lines (push-pull outputs) As a rule these lines can be used as input or output lines. As soon as ports 1 to 4 are used as system bus, they are lost as I/O-channels. However, a total of 48 port lines (24 inputs and outputs each) can be reconstructed without difficulties (1 housing for 8 lines), if the additional 6 I/Olines of the CCU 3000, CCU 3001 are switched into the port select mode. They then represent the select lines of the original ports 1 to 3. Each line can be defined as I/O or port select line separately. In the I/O-page three bytes are needed. 5 2.5. PORT 1 to PORT 3, PORT 6 to PORT 8 8 ports belong to the system, of which 5 are 8 bits wide, one 6 bit, one 4 bit and one 1 bit wide. All port lines of PORTS 1 to 3 and 6 to 8 can be used as inputs or outputs independently from each other. One register per port defines the direction. PORT1 to PORT3 have push-pull outputs and PORT6 to PORT8 have open drain outputs. Even a line defined as output can be read, the pin level being important. This property makes it possible for the software to find desired and undesired short circuits. Each port reserves a byte for the direction register and the data in the I/O page. If the corresponding bit in the direction register is set to 0, the output mode is switched on. After a reset, all bits of a direction register are set to 1. The falling edge of bit 7 of PORT 8 generates interrupts if the priority of the corresponding interrupt controller source (7) is not set to 0.
Page 0 offers a particularly fast access to the 65C02 and is therefore very valuable for fast, compact programs. Page 1 contains the stack and must therefore also have RAM. The remaining RAM-memory follows in pages 3, 4, 5, 6, as page 2 is reserved as I/O address space. The RAM can be kept in the stand-by mode via stand-by pin. 2.3. CPU The CPU core is fully compatible with the 65C02 microprocessor. However, not all the pins of the 65C02 processor are accessible for the user outside the chip. One switch in the control register allows the CPU to be switched off, so that an external processor can take over its tasks. This external processor can of course also be an in-circuit emulator, which makes near-hardware emulation possible, even though the status and control lines of the internal CPU are not accessible. If an external processor is used, all hardware blocks of the chip are as accessible to it as if it were the internal CPU. 2.4. Clock Generator An integrated two-pin oscillator generates the clock for the microcontroller. The frequency created by the oscillator can be programmed to be reduced with a divider by the factor 1 ... 255. This enables the user to decrease the current consumption by the controller by reducing the working frequency as well as to increase the access time for the (slower) external memory. This divider contains the value 4 after a reset, so that the system can also start with a slow external memory. If the mask-option OSC is set (EMU version), a switch in the control register makes it possible to receive the internal clock 2 at XTAL2. In this case the oscillator must be external and the clock must be fed to the pin XTAL1. In this way, the user gets a time reference for internal operations in the microcomputer. This is especially important with the interrupt controller. The production version of the CCU does not have this function! MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
Mode 1 bit 5,4,3,2,1,0 Switch I/O - port select mode 0... I/O line (default) 1... port select direction switch for I/O lines 5 ... 0 1... input (default) 0... output Data 3 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 I/O 5 or RDPort 1 I/O 4 or WRPort 1 I/O 3 or RDPort 2 I/O 2 or WRPort 2 I/O 1 or RDPort 3 I/O 0 or WRPort 3
Direction 2 bit 5,4,3,2,1,0
D0...D7
Data valid
WR Port 1...3
RD Port 1...3 Fig. 2-1: Timing diagram
D0...D7 CCU 3000, CCU 3001 Port 1 in P55 P54 P53 P52 Port 1 out Port 2 in
e.g. `244 e.g. `374
D0...D7
Memory
OE
Port 2 out Port 3 in Port 3 out
P51 P50 P76 R/W
Fig. 2-2: External reproduction of ports 1 to 3
2.8. Special Mode of Port 7 Each line of port 7 can be switched independently into a special mode. This mode is selected by the mode control register. After reset this register is set to 0 (= Port mode). A "1" in this register turns this line into the special mode. As the control signals are all outputs, the direction for those lines must be defined as outputs (reset condition = inputs) 6
Special Mode of P77 P76 P75 ...P70
Function Power-down control for ext. memory R/W output 6 bit banking addresses with common home bank logic
All special mode signals have push-pull outputs. (Port mode: open drain). MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
2.8.1. Power-down Control External Memory (Special Mode P77) In many applications the power consumption of the controller should be reduced when the system goes into standby mode. The programmable clock of the CCU allows this, but external memories do not automatically reduce their power consumptions when the access speed is slower. These devices need a separate control signal for power down. Special out of P77 delivers such a signal. It is low for the last two XTAL cycles before, and 0.5 cycles after the rising edge of the internal PHI2 clock. This guarantees a wake-up and address time of 2 cycles and a maximum active time of 2.5 clock cycles for each PHI2 period. At higher speeds the P77 special out stays low. dresses 1 to 63. This bank is used for CPU accesses from 8000H to FFFFH. Low accesses are always done to bank 0, independent of the data of Port 7. Note: - all upper banks must contain the interrupt vectors. Bank 0 must have the control word and reset vector. - during and after reset P7 is in the Tristate-Port-Mode. To make sure that the control word and the reset vector can be accessed use high impedance pull-down resistors on all special-out P7 lines. The control word and the reset vector are then accessed out from bank 0. The init routine (where P7 will be defined as special out) must be in bank 0. 0000H FOSC Internal 2 P77 2 cycles 2.5 cycles Fig. 2-3: Power-down control Please note that during and after reset P77 is a port line (= tristate) until the special mode and the direction register is set by software. A pull-down resistor on the powerdown input of the memory is necessary to allow the CCU the access to the control word and the first instructions. 2.8.2. R/W Output (Special Mode P76) This is the negated R/W-line of the CPU. Can be used for CE or OE control on memories. With a pull-down resistor on this pin it is active during RESET. 2.8.3. Banking Address (Special Mode P70 to P 75)
A0 A0 A14 A15 A16 A17 A18 A19 A20
RAM I/O RAM
Bank 0 Home bank 7FF9H 7FFCH 7FFDH 7FFFH 8000H ROM Control word if pull-down resistors are used for all bank Reset address outputs Reset
Bank 1
2
3
4
5
Bank 63
FFFFH
INT vectors in all Banks 1 to 63
Fig. 2-4: Memory Map, up to 2 MByte
Banking is done in 32 KByte banks. The first bank (000H to 7FFFH) includes the RAM, the I/O-page and ROM (all other locations) and is used as a home-bank for the banking controller, interrupt routines, common subroutines etc. The second half of the address space (8000H to FFFFH) is banked. In the special mode of Port 70 to 75 the content of the data register is output as long as the address A15=1. A low level of A15 forces all special outs of P70 to P75 to become `0'. The data register can contain the bank adMICRONAS INTERMETALL
CCU
A14 A15 open P70 P71 P72 P73 P74 P75
Memory
Fig. 2-5: Banking with 32 kByte banks 7
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
2.9. Reset Function The internal reset provides a correct basic setup of the complete hardware on the chip. For this the internal control register is loaded during reset. One reserved byte in the ROM is accessed by the reset circuit and its content is copied into the control register. The internal voltage supervision resets the IC if the voltage is too low. The reset pin is also used as output for internal reset sources (watchdog, power-down detector, clock supervisor). Internal resistors limit the maximum current. dictated by reset. The switches have the following functions: bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 to 7 CPU_disable RAM_disable ROM_disable R/W-mode P4 Bus external set to 1 (low active) (low active) (low active) (low active) (low active)
2.10. Control Register (address 201H) This is a combination of control switches in an 8-bit register. During reset it is loaded with the contents of the address FFF9H, but it can also be read and written via software. The controller starts operation with the setting
The setting at the R/W-pin decides whether the control word is read internally or externally. Bit 0 to bit 2 are the switches which can disable RAM, ROM and CPU. For external access a pull-up resistor must be connected to the R/W pin (CCU 3001). Bit 4 switches P1, P2 and P3 into the system bus mode. If the internal CPU is active, the direction of the data bus drivers is automatically set correctly, so that no additional decoding is necessary. Bit 3 switches P4 into the R/W mode. If no external write access is necessary, (ext. EPROM), P4 can stay in the port mode.
C1 = 22 p X1
C2 = 22 p X2 CCU 3000, CCU 3001 Prescaler 2
OSC
D0...D7 Supervision Clock Voltage Detector VSUP 300 k RESOUT RES RESIN DOGBIT RESET Watchdog POR CLKRES Reset + Control- word Logic A0...A15 Internal Reset
Fig. 2-6: Oscillator and reset 8 MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
tOSC = start-up time oscillator
VSUP
1 fOSC
tOSC
2
3
4
5
6
int. Reset
A0...A15
FFF9
D0...D7 RES (without ext. C) Fig. 2-7: Power-on sequence
Control Word
normal operation
fOSC A0...A15 D0...D7 int. Reset RES FFF 9 Control Word
1
2
3
4
5
6
VSUP 2
normal operation Fig. 2-8: External reset sequence
MICRONAS INTERMETALL
9
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
2.11. Interrupt Controller The most important properties of this controller are: - 8 sources - 8 freely programmable priorities for every source - maximum delay of 3 clock cycles - vectorized interrupts, i.e., automatically the correct routine is accessed - also to be used for external CPU - option: disable after interrupt (resettable by software) Running service routines are only interrupted if interrupts are enabled and a request of higher priority arrives. All others are stored and executed when interrupts of higher priority have been finished. Priority 0 means that the corresponding interrupt is disabled. (Priorities 1-7 lead to interrupts). One property of the controller is that the CPU is not modified, but vectorization takes place all the same. Thus the use of this controller is also possible for external CPUs (emulator!). Solely the return from a service program differs slightly in software from the methods normally used for the 65C02. The last command before the "RTI" must be a write operation into the return register of the controller. This tells the controller that the service routine has been completed. Apart from this return register the controller occupies further 5 bytes. One of these serves as a control byte, the others incorporate the priorities for 8 sources. The controller therefore needs 6 bytes of the I/O-page. The control byte comprises: bit 0 bit 1 bit 2 bit 3 bit 4 CLEAR_ALL_REQUESTS ALLOW_ONE_INTERRUPT DISABLE_INTERRUPTS DISABLE_AFTER_INT RESET_CONTROLLER (low active) (low active) (low active) (low active) (low active) bit 3, 2, 1, 0 sends an appropriate signal. This has the same impulse length as the 65C02. Each of the 4 priority registers contains the priorities for 2 interrupt sources. bit 7, 6, 5, 4 Priority for sources 8, 6, 4, 2 Priority for sources 7, 5, 3, 1
To connect an external CPU (emulator) with the controller, only two ICs of the 74-family are needed. 2 ADB
DB
CTRLQ Fig. 2-9: Dynamic control signals interrupt Bits 0, 1, 4
2 ADB
All bits reset to 1 (inactive). CLEAR_ALL_REQUESTS clears all interrupt flags at the same time. ALLOW_ONE_INTERRUPT is used in connection with the DISABLE_AFTER_INT (bit 3), to allow access to the next interrupt. DISABLE_INTERRUPT does not allow any interrupts, the request flags are set however. With the exception of bits 3 and 2 (DISABLE_INTERRUPTS, DISABLE_AFTER_INT) these are all dynamic signals, that is, the write process itself DB
CTRLQ Fig. 2-10: Static control signals interrupt Bits 2, 3
10
MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
Priority Latches Int.1 clr 1 NMI Int.2 clr 2 A>B Int.3 clr 3 Int.4 clr 4 Int.5 clr 5 Int.6 clr 6 Int.7 clr 7 Int.8 clr 8 Reset D0...D7 Fig. 2-11: Interrupt controller clk A Comp. B CLR `0` `1` to IR Circuit IR
CPU dis
CLR Prior. Dec.
push Prior. of int. Source of int. pop Stack A=B Comp. B RETURN
CLR clr_1 1 of 8 Decod. en Vector Table FFFA + FFFB A0...A15
clr_8 Clear Request
CLR
MICRONAS INTERMETALL
11
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
XTAL2 XTAL1 CLK in IR clr Q D D Q
RDY 2 in
NMI clr CCU 3000, CCU 3001 EMU Version OR Counter 21 Ext. CPU or Emul.
A0 A0 ...A15 A15 D0 D0 ...D7 D7 ROM/RAM Fig. 2-12: Using an external CPU
en
A0 A15 D0 D7
2.12. IM Bus Interface The IM bus has been improved in its characteristics for the CCU 3000, CCU 3001. In comparison to the interface of the CCU 2000 series it differs in: - multimaster ability - 3 slave registers (8 bit wide) - higher speed possible
in the system) will be the same. The handshake amongst these is realized in software, and one register each is reserved for the device address, the request and the data to be transported. The data rate can now be adjusted per software. It is possible to attain 1 MBit/s, if the bus participants in question are devised to support this rate. Also the actual realization of the bus can forbid such a high data rate. The IM bus interface needs external pull-up resistors. In the I/O-page the IM bus interface reserves 8 bytes:
The multimaster ability permits the use of several CCUs on the same IM bus without impeding each other. Specially in add-on systems or systems with need of high computing power and/or I/O requirements, this offers great advantages. If several CCUs are admitted in a system, it must be ascertained that these can communicate with each other. A slave IM bus interface has been installed for this purpose. Parallel to the lines of the master, three completely independent receiver registers have been installed. All of these are constantly alert, whether the master itself is active or not. As all CCUs have the same IM bus addresses for these registers, the contents of these registers (that is, for all CCUs that are 12
3 bytes 1 byte 2 bytes 1 byte read:
slave receiving registers (read) master address (write) master data register (read/write) control register (read/write) bit 0 0... IM bus master ready 1... IM bus master busy bit 1 1 Byte received in slave register 1 (may generate interrupt) bit 2 IM-bus 1 control and status (may generate interrupt) bit 3 Word 3 Received (may generate interrupt) MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
1... Write 8 bit 1... Write 16 bit 1... Read 8 bit 1... Read 16 bit 1 byte Data rate (5 bits) = fosc 4. n Only one of the bits 0 to 3 in the control register should be set. If all bits are set to `0`, a reset of the interface is CPU data bus Slave 1 Slave Interface IM Bus addresses 2, 3 and 4 ID Data CLK write: bit 0 bit 1 bit 2 bit 3 done, thus deleting telegrams still waiting for access to the bus. The IM bus addresses for the slave registers are: Slave register 1 2 3 IM bus address 02 H 03 H 04 H
Slave 2
slave register 1 (IM Bus address 02H) received data (1 byte)
Slave 3
INT
INT 3 Contr.
Mode Master Ready
4
transmission completed
Data
Master Interface Addr.
Rate
Data rate n
Data rate: fIM = Fig. 2-13: IM bus interface
fosc ; 4 .n
n=
fosc 4 . fIM
MICRONAS INTERMETALL
13
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
2.13. Multifunctional Timer The multifunctional timer for the CCU 3000, CCU 3001 has quite an unusual structure. It can serve as: - event counter - frequency counter - pulse-length meter - timer - rate multiplier - PWM - asynchronous, serial interface Each timer has a reserved pin and an interrupt. The pin is either input or output, depending on its function. Used as an output it has a push-pull structure. The timer consists of three main parts: - start and stop detector - internal time reference - accumulator and arithmetic unit The start and stop detector controls the internal pulse generator to synchronize counter and meter operations. The timer itself does not consist of a counter circuit, but of an accumulator and an adder. This configuration works as a counter with adjustable step length, as a shift register, as a PWM and as a rate multiplier. Change-over of operation modes can easily be effected. Each of the multifunctional timer circuits of the CCU is realized as two 8-bit accumulators. In addition, there is In addition to its parallel byte connections, the adder registers have serial inputs and outputs. A serial clock shifts its contents. To hit the middle of serial data, the timer's prescaler has a half load feature, controlled with bit 1 in control byte 1. Fig. 2-14 shows a detailed diagram of the high part of the reloadable accumulator and its adder register. For examples of timer applications please refer to "Application Note CCU 3000/3001 Timers". a separate adder register for each of them. Both the accumulator and the adder may be accessed by the CPU via data bus. The accumulator has a shadow register the CPU may write to and the adder bus register may be read and written to. While the adder register forms one side of the adder, the other side is either the output of the adder or the content of the accu shadow register. With every accu clock pulse either of these bytes is used. If no "LOAD" signal is active, the adder output is used. With "LOAD" active, the following accu clock pulse uses the content of the accu shadow register as adder input. The "LOAD" signal is derived from 1 out of 4 sources, selectable with bits 3 and 4 of control byte 3. Accu clock is selectable with bits 1 and 2 in control byte 2. Instead of the content of the adder register, accessible by the CPU, a hard-wired `-1' may be used as input of the other side of the adder (bits 1 and 2 in control byte 3). By adding `-1' to the accu's content, the adder works as a standard down counter. With specific "READ LATCH" signals (control byte 2, bits 3, 4 and 5) and using the adder register as adder input, its content defines the step width of the counter.
14
MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
D0 ... D7
Start bit 8-bit latch
0 1
WR
WR shadow register
set to `0' during LOAD active (LD = 0)
accu clock
REACCU C reloadable accumulator 8-bit latch CI
CI
CO1
CO
LD OUT IN
OUT1
1 0
-1
control reg. 3, bit 2
latch clock
8-bit latch
EN EN
EN
write bus register (adder) low byte
read bus register (adder) low byte
D0 ... D7 Fig. 2-14: Reloadable accumulator
MICRONAS INTERMETALL
15
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
Apart from the start values for the counter and adder registers, three control registers shift the timer into the preselected function. Registers to control the timer: 2 bytes prescaler high and low byte (read/write) (read: prescaler) (write: prescaler and reload register) 2 bytes accu high and low byte (write) (write: accu and reload register) 2 bytes adder register high and low byte (read/write) 3 bytes control register 1 to 3 (write)
1/2 LOAD EDGE
+
D
CLR
Q Q
+D START
CLR D0...D7 D0...D7 Q
WR
WR
D Q
+ STOP +
fosc
REACCU A CO CI
LOAD LSB IN MSB
REACCU CI B CO
LOAD LSB IN MSB
+
CLR
2 CLOCK
PIN PIN
STOP
Presc. in
Presc. out
Fig. 2-15: Prescaler timer, start/stop logic 16 MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
Presc. in Presc. out
PIN CO 2 ACCU_ clk
Stop
CO 1 INTER INT
D0...D7
PIN Startbit LOAD CI WR REACCU C LD OUT IN CO1 CO2
D0...D7
WR REACCU Cl LD OUT IN
LONG
PIN PIN D CO 2
Reg
CO 1
CO1
CO2 RD LATCH
PIN PIN Presc.in Presc. out
IN1 OUT1 IN2 OUT2 serial clock BUS REGISTER (ADDER REGISTER) latch clock Serial Serial Serial Serial
WR1 RD1 WR2 RD2 IN OUT Mode IN 2 -11 -12
PWM
CO PIN
open
from control word
SO PINOUT D SET Q
Q Q CLR
D
Q CLR
D
+
D0...D7
D
Q CLR
Reset active Fig. 2-16: Timer
Startbit
Startbit generator
Reset active
The three control registers control the internal switches of the timer: Control register 1 Control register 2
bit 7 bit 6, 5
SERIAL_2 Clock
bit 4 bit 3, 2
Stop Start
bit 1 bit 0
1/2 load Edge detector
Second Serial Input Level 00.. PIN 01.. fosc. 10.. 2 11.. disable clock 0... stop disabled 1... carry out accu 00.. always active 01.. edge 10.. PIN 11.. PIN 0... disabled 1... active 0... rising 1... falling
bit 7, 6
PIN_out
bit 5, 4, 3
Read_Latch
bit 2, 1
accu clock
bit 0
long
00.. 01.. 10.. 11.. 000. 001. 010. 011. 100. 101. 110. 00.. 01.. 10.. 11.. 0... 1...
open serial out PWM out carry accu D open carry accu C carry accu D PIN PIN prescaler output prescaler input prescaler input prescaler output PIN PIN open carry out accu C carry in accu D 17
MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
Control register 3
bit 7, 6, 5
INTER
bit 4, 3
LOAD
000. 001. 010 011. 100. 00.. 01.. 10.. 11..
open PIN PIN carry accu C carry accu D open carry accu C carry accu D Reg
bit 2
-11
0... 1...
bit 1
-12
0... 1...
bit 0
Serial mode
0... 1...
ACCU C input = bus reg. ACCU C input = -1 ACCU D input = bus reg. ACCU D input = -1 mode off mode on
18
MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
2.14. Watchdog - not active after Reset - activated when written, cannot be stopped via software - to retrigger, the watchdog period negated bit by bit must be rewritten within the preset space of time (first write event is also counted) - triggers reset, the software can identify if Reset was generated by watchdog - 16 ms to 4 s time-out for 4 MHz system clock The nearest integer value is 122. Because a 0 loaded into the counter divides by 1, already, the watchdog counter has to be programmed with 122-1 = 121. With the formula above
n = 121 = 1s * 8 MHz/65536 - 1 The software sequences in Assembler could look like this: Definitions:
This counter circuit offers hardware support for software problems. It is disabled after reset and enabled with the first write of the desired time value into its register. The value to program is calculated by n = TWD * fsystem / 65536 - 1 with n = watchdog counter value to be programmed for TWD = the desired watchdog time and fsystem = system frequency. Remarks: a) To prevent the generation of a `RESET' by the watchdog before it could be retriggered by the software, watchdog counter values less than 2 should not be programmed. b) The system clock as input of the watchdog counter is influenced by the system clock prescaler, determining the CPU speed (register addr. 200 H). Software can't stop this counter but has to retrigger it by writing the inverted value (one's complement) of the preceding written pattern into its register, which makes unwanted retrigger loops of disturbed software unlikely. These writes have to occur within the time frame (8 ms to 2 s at 8 MHz system clock), defined with the first write. If no write with the expected pattern occurs within the programmed time period, the watchdog circuit resets the CCU at the end of the time period. There will also be a watchdog reset if another pattern is written instead of the expected one. The software can detect if a reset was generated by the watchdog: Bit 0 of the watchdog register is `0' if the last reset was generated by the watchdog. This bit is reset only with an external reset, e.g. generated by power-on. Examples: To set a cycle time of 1 second with 8 MHz system clock the value is 121. This value is calculated as follows: system frequency: 8 MHz watchdog cycle time: 65536 / 8 MHz = 8.192 ms, counter value: 1 s / 8.192 ms = 122.07. MICRONAS INTERMETALL
;constants: WATCHDOG_TIME ;CCU I/O-address: watchdog_address ;variable: watchdog_value
EQU EQU EQU
121 202H 30H ;(address ; of free RAM location)
Example 1: During initialization the watchdog is filled with the desired time-value:
LDA STA STA #WATCHDOG_TIME watchdog_address watchdog_value
;memorize ; watchdog pattern
In the main loop of the program the watchdog has to be retriggered cyclically:
LDA EOR STA STA watchdog_value #FFH watchdog_address watchdog_value ;invert bits ;memorize new ; watchdog pattern
Example 2: If an interrupt function occurs cyclically, one value may be programmed in the interrupt service routine, while the other is written in the main loop. So both the continuity of executing the interrupt service and the main loop are checked: During initialization the watchdog shadow variable is filled with the desired time-value:
LDA STA #WATCHDOG_TIME watchdog_value ;memorize ; watchdog pattern
Sequence in the interrupt function:
LDA CMP BEQ ; STA watchdog_address EOR #$FF STA watchdog_value SKIP_IRQ_WD ... watchdog_value #WATCHDOG_TIME SKIP_IRQ_WD
19
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
Sequence in the main loop:
LDA CMP BNE ; STA watchdog_address EOR #$FF STA watchdog_value SKIP_WD ... watchdog_value #WATCHDOG_TIME SKIP_WD
Remark: It is important to program the watchdog register with the new value before this value is memorized in the shadow variable, because this procedure could be interrupted by the interrupt, which will program the watchdog with the complementary value.
D0...D7 latch = = D Q CLR SWATCH R/W + D Q CLR Q latch RESET active RES_DOG 2
RES_DOG_1
=
8-bit counter
POWER down CLR 16-bit 2
EN R/W SWATCH
D0
Fig. 2-17: Watchdog
2 D0...D7
SWATCH RES_DOG_1 R/W
Trigger watchdog is retriggered
Fig. 2-18: Timing watchdog 20 MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
2.15. IR-Input The IR-interface consists of two parallel edge detectors which trigger the rising and falling edge. The respective state of the rising edge triggered flip-flop can be read from D0 (triggered positively), or D1 (triggered negatively). Any read event via the CPU deletes both flipflops. D2 reflects the status of the IR pin, D3 to D7 are set to 0. If the CPU is switched off, the IR-Interface is no longer available, as the IR pin is used as output for the interrupt controller. For use as an emulator this function has to be rebuilt externally. The I/O-address designed for the IRINPUT is treated as an external address when the CPU is switched off, so that the software can remain untouched. 2.16. Mask Options There are two mask options: OSC option: if this option is set, X1 and X2 can be used as clock input and output or as XTAL pins, (depending on control word bit 5) if this option is set, the reset sources Power on and Clock Supervision are disabled with bit 0 of the test register 2FFH. Default = enabled).
RES option:
In the production version none of the options is set, in the EMU version both are set.
CPU dis `1' IR `0'
CLR
D0 RDIR
CLR
D1 D2 from Interrupt Controller
Fig. 2-19: IR input
MICRONAS INTERMETALL
21
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
3. Definitions 3.1. Interrupt Definitions Interrupt 0 1 2 3 4 5 6 7 RESET Source TIMER1 TIMER2 TIMER3 IM-BUS1, Master IM-BUS1, Slave IM-BUS2, Master IM-BUS2, Slave P87 Vector (low, high byte) FFF6, FFF7 FFF4, FFF5 FFF2, FFF3 FFF0, FFF1 FFEE, FFEF FFEC, FFED FFEA, FFEB FFE8, FFE9 FFFC, FFFD 21AH 21CH 21DH 21EH 21FH 220H 221H 222H 223H 224H 225H 226H 228H 229H 22AH 22BH 22CH 22DH 22EH 22FH 230H 232H 233H 234H 235H 236H 237H 238H 239H 23AH 23CH 23DH 23EH 23FH 240H 241H 242H 243H 244H 245H 246H 247H 249H 24AH 24BH 24CH 24EH 250H 2E0H to 2E7H 2FEH 2FFH IM-Bus 1 slave 3, IM-Bus address 04 Interrupt controller control byte Interrupt controller return byte Interrupt controller priorities source 0 & 1 Interrupt controller priorities source 2 & 3 Interrupt controller priorities source 4 & 5 Interrupt controller priorities source 6 & 7 Timer 1 control byte 1 Timer 1 control byte 2 Timer 1 control byte 3 Timer 1 prescaler low byte Timer 1 prescaler high byte Timer 1 accu low byte Timer 1 accu high byte Timer 1 adder low byte Timer 1 adder high byte Timer 2 control byte 1 Timer 2 control byte 2 Timer 2 control byte 3 Timer 2 prescaler low byte Timer 2 prescaler high byte Timer 2 accu low byte Timer 2 accu high byte Timer 2 adder low byte Timer 2 adder high byte Timer 3 control byte 1 Timer 3 control byte 2 Timer 3 control byte 3 Timer 3 prescaler low byte Timer 3 prescaler high byte Timer 3 accu low byte Timer 3 accu high byte Timer 3 adder low byte Timer 3 adder high byte Port 6 Data Direction Register Port 6 Port 7 Data Direction Register Port 7 Port 8 Data Direction Register Port 8 IM-Bus 2 control & status IM-Bus 2 transfer rate IM-Bus 2 master address IM-Bus 2 master data low IM-bus 2 master data high IM-bus 2 slave 1, IM address 02 IM-bus 2 slave 2, IM address 03 IM-bus 2 slave 3, IM address 04 External addresses, used for EMU boards Reserved, do not use Reserved for testing purposes
3.2. Memory Mappings RAM ROM Control byte I/O 0000H to 01FFH 0300H to 063FH 8000H to FFFFH FFF9 0200 to 02FF Page 0, 1 Page 3, 4, 5, 6 (CCU3001 only)
3.3. I/O Definitions Address 200H 201H 202H 203H 204H 205H 206H 207H 208H 209H 20AH 20BH 20CH 20DH 20FH 210H 211H 213H 214H 215H 216H 218H Function Clock frequency Control register Watchdog Port 1 Data Direction Register Port 1 Port 2 Data Direction Register Port 2 Port 3 Data Direction Register Port 3 Port 4 Data Port 5 Mode Register Port 5 Direction Register Port 5 Data IR-Input Port 7 Mode Register IM-Bus 1 control and status IM-Bus 1 data transfer rate IM-Bus 1 master address IM-Bus 1 master data low byte IM-Bus 1 master data high byte IM-Bus 1 slave 1, IM address 02 IM-Bus 1 slave 2, IM-Bus address 03
22
MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
4. Specifications 4.1. Outline Dimensions
2.4 1+0.2 x 45 9 10 2 9 25 +0.25 0.711 24.2 0.1 2 1 2 61 60 0.457 2.4 1.27 0.1 15 9 24.2 0.1 0.1 16 x 1.27 0.1 = 20.32 0.1 16 x 1.27 0.1 = 20.32 0.1 1.27 0.1 1.2 x 45
26 27 25 +0.25 43
44 1.9 1.5 4.05 4.75 0.15
Fig. 4-1: 68-Pin Plastic Leaded Chip Carrier Package (PLCC68) Weight approximately 4.8 g Dimensions in mm
VSUP GND X2 X1 V Stand-by RES DAT_IM1 ID_IM1 CLK_IM1 P67 P66 P65 P64 P63 P62 P61 P60
DAT_IM2 ID_IM2 Clk_IM2 TIMER1 TIMER2 TIMER3 IR P4 (R/W) P10 (D0) P11 (D1) P12 (D2) P13 (D3) P14 (D4) P15 (D5) P16 (D6) P17 (D7) P20 (A0)
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
9
8
7
6
5
4
3
21
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
P87/INT P83 P82 P81 P80 P77 P76 P75 P74 P73 P72 P71 P70 P55 P54 P53 P52
CCU 3000, CCU 3001
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 P21 (A1) P22 (A2) P23 (A3) P24 (A4) P25 (A5) P26 (A6) P27 (A7) P30 (A8) P31 (A9) P50 P37 (A15) P36 (A14) P35 (A13) P34 (A12) P33 (A11) P32 (A10) P51
Fig. 4-2: Pinning of the CCU 3000, CCU 3001 in PLCC68 package
MICRONAS INTERMETALL
0.2
23
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
15 28 33 4 0.1
4.2. Pin Configuration
64
1
32 3.8 0.1 19.3 0.1 18 0.1 P11 (D1) 4.8 0.2 P10 (D0) P4 (R/ W) IR 0.1 1 0.05 1.778 0.05 0.27 0.1 20.1 0.5 TIMER3 TIMER2 TIMER1 CLK_IM1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P12 (D2) P13 (D3) P14 (D4) P15 (D5) P16 (D6) P17 (D7) P20 (A0) P21 (A1) P22 (A2) P23 (A3) P24 (A4) P25 (A5) P26 (A6) P27 (A7) P30 (A8) P31 (A9) P32 (A10) P33 (A11) P34 (A12) P35 (A13) P36 (A14) P37 (A15) P50 P51 P52 P53 P54 P55 P70 P71 P72 P73
57.7 0.1 (1)
3.2 0.2
0.457
1.29
31 x 1.778 = 55.118 0.1
1.9
Fig. 4-3: 64-Pin Plastic Shrink Dual Inline Package (PSDIP64)1) Weight approximately 9.0 g Dimensions in mm
ID_IM1 DAT_IM1 RES VStand-by X1 X2 GND VSUP
64
33
P67 P66 P65 P64 4.25 0.15
1 (0.51 min.)
32
P63 19.3 0.1 17 0.25 5.2 0.5 P62 P61 P60 P87 P82 0.25 0.06 20.5 max. P81 P80 P77 P76 P75
58 0.3
3.25 0.3
1.778
0.46 0.1 O 0.25 M
Fig. 4-4: 64-Pin Plastic Shrink Dual Inline Package (PSDIP64F)2) Weight approximately 9.0 g Dimensions in mm
1) 2)
P74
Fig. 4-5: Pinning of the CCU 3000, CCU 3001 in PSDIP64 and PSDIP64F package
PSDIP64 = Manufactured in Freiburg PSDIP64F = Second Source
24
MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
4.3. Pin Connections and Short Descriptions DA ID CL X = IM bus data line of external devices = IM bus ident line of external devices = IM bus clock line of external devices = obligatory; connections depend on application
Pin No.
68-pin PLCC 64-pin SDIP
Connection
I: Input O: Output
Pin Name
Short Description
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
16 15 14 13 12 11 10 9 8 - - - 7 6 5 4
+5V GND Crystal Crystal +3V +5V X DA ID CL DA ID CL X X X external infrared receiver X X X X X X X to
I I I/O I I I/O I/O O O I/O O O I/O I/O I/O I
VSUP GND X2 X1 VStand-by RES DAT_IM1 ID_IM1 CLK_IM1 DAT_IM2 ID_IM2 CLK_IM2 TIMER1 TIMER2 TIMER3 IR
Supply Voltage Ground Crystal connector 2 Crystal connector 1 Standby Supply Voltage Reset input/Reset output IM bus 1 data signal IM bus 1 ident signal output IM bus 1 clock signal output IM bus 2 data signal IM bus 2 ident signal output IM bus 2 clock signal output Timer 1 signal Timer 2 signal Timer 3 signal Infrared signal input
17 18 19 20 21 22 23
3 2 1 64 63 62 61
I/O (O) I/O (I/O) I/O (I/O) I/O (I/O) I/O (I/O) I/O (I/O) I/O (I/O)
P40 (R/W) P10 (D0) P11 (D1) P12 (D2) P13 (D3) P14 (D4) P15 (D5)
Port 4 bit 0 (CPU read/write) Port 1 bit 0 (CPU data bus bit 0) Port 1 bit 1 (CPU data bus bit 1) Port 1 bit 2 (CPU data bus bit 2) Port 1 bit 3 (CPU data bus bit 3) Port 1 bit 4 (CPU data bus bit 4) Port 1 bit 5 (CPU data bus bit 5)
MICRONAS INTERMETALL
25
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
Pin No.
68-pin PLCC 64-pin SDIP
Connection
I: Input O: Output
Pin Name
Short Description
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
X X X X X X X X X X X X X X X X X X X X X X X X X X X X
I/O (I/O) I/O (I/O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O)
P16 (D6) P17 (D7) P20 (A0) P21 (A1) P22 (A2) P23 (A3) P24 (A4) P25 (A5) P26 (A6) P27 (A7) P30 (A8) P31 (A9) P32 (A10) P33 (A11) P34 (A12) P35 (A13) P36 (A14) P37 (A15) P50 (RD Port 1) P51 (WR Port 1) P52 (RD Port 2) P53 (WR Port 2) P54 (RD Port 3) P55 (WR Port 3) P70 (Memory Bank Address 0) P71 (Memory Bank Address 1) P72 (Memory Bank Address 2) P73 (Memory Bank Address 3)
Port 1 bit 6 (CPU data bus bit 6) Port 1 bit 7 (CPU data bus bit 7) Port 2 bit 0 (CPU address bus bit 0) Port 2 bit 1 (CPU address bus bit 1) Port 2 bit 2 (CPU address bus bit 2) Port 2 bit 3 (CPU address bus bit 3) Port 2 bit 4 (CPU address bus bit 4) Port 2 bit 5 (CPU address bus bit 5) Port 2 bit 6 (CPU address bus bit 6) Port 2 bit 7 (CPU address bus bit 7) Port 3 bit 0 (CPU address bus bit 8) Port 3 bit 1 (CPU address bus bit 9) Port 3 bit 2 (CPU address bus bit 10) Port 3 bit 3 (CPU address bus bit 11) Port 3 bit 4 (CPU address bus bit 12) Port 3 bit 5 (CPU address bus bit 13) Port 3 bit 6 (CPU address bus bit 14) Port 3 bit 7 (CPU address bus bit 15) Port 5 bit 0 (CCU read Port 1) Port 5 bit 1 (CCU write Port 1) Port 5 bit 2 (CCU read Port 2) Port 5 bit 3 (CCU write Port 2) Port 5 bit 4 (CCU read Port 3) Port 5 bit 5 (CCU write Port 3) Port 7 bit 0 (Memory Bank Address 0) Port 7 bit 1 (Memory Bank Address 1) Port 7 bit 2 (Memory Bank Address 2) Port 7 bit 3 (Memory Bank Address 3)
26
MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
Pin No.
68-pin PLCC 64-pin SDIP
Connection
I: Input O: Output
Pin Name
Short Description
52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
32 31 30 29 28 27 26 - 25 24 23 22 21 20 19 18 17
X X X X X X X X X X X X X X X X X
I/O (O) I/O (O) I/O (O) I/O (O) I/O I/O I/O I/O I/O /I I/O I/O I/O I/O I/O I/O I/O I/O
P74 (Memory Bank Address 4) P75 (Memory Bank Address 5) P76 (R/W) P77 (Power-Down Control) P80 P81 P82 P83 P87/INT P60 P61 P62 P63 P64 P65 P66 P67
Port 7 bit 4 (Memory Bank Address 4) Port 7 bit 5 (Memory Bank Address 5) Port 7 bit 6 (CPU read/write) Port 7 bit 7 (Power-Down Control) Port 8 bit 0 Port 8 bit 1 Port 8 bit 2 Port 8 bit 3 Port 8 bit 7 /interrupt input Port 6 bit 0 Port 6 bit 1 Port 6 bit 2 Port 6 bit 3 Port 6 bit 4 Port 6 bit 5 Port 6 bit 6 Port 6 bit 7
MICRONAS INTERMETALL
27
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
4.4. Pin Descriptions CCU 3000, CCU 3001 Pin Descriptions. Pin numbers refer to the 68-pin PLCC housing. The functions of some pins are influenced by bit 4 of the CCU control register (addr. 201H, copied from FFF9H at reset: CCU control register bit 4 = `1' switches the CCU in Port Mode , CCU control register bit 4 = `0' switches the CCU in Bus Mode. In addition, some port bit functions may be changed between Normal Mode and Special Mode by setting the specific bit in its port mode registers. Pin 1: Vsup: +5V power supply Pin 2: GND: Digital ground Pin 3: X2: Second Crystal connector Pin 4: X1: First Crystal connector Pin 5: VStand-by: +5V Stand-by Supply Voltage Pin 6: RES\: CCU Reset input / output (open drain) Pin 7: DAT_IM1: IM bus 1 data signal (I/O) Pin 8: ID_IM1: IM bus 1 ident signal output Pin 9: CLK_IM1: IM bus 1 clock signal output Pin 10: DAT_IM2: IM bus 2 data signal (I/O) Pin 11: ID_IM2: IM bus 2 ident signal output Pin 12: CLK_IM2: IM bus 2 clock signal output Pin 13: TIMER1: Timer 1 signal (I/O) Pin 14: TIMER2: Timer 2 signal (I/O) Pin 15: TIMER3: Timer 3 signal (I/O) Pin 16: IR: Infrared signal input Pin 17: P40 or R/W\: in Port Mode: Port 4 Bit 0 in Bus Mode: CPU read/not write output Pin 18 : P10 or data bit 0: in Port Mode: Port 1 Bit 0 in Bus Mode: CPU data bit 0 Pin 19 : P11 or data bit 1: in Port Mode: Port 1 Bit 1 in Bus Mode: CPU data bit 1 28 Pin 32 : P26 or address bit 6: in Port Mode: Port 2 Bit 6 in Bus Mode: CPU address bit 6 Pin 33 : P27 or address bit 7: in Port Mode: Port 2 Bit 7 in Bus Mode: CPU address bit 7 Pin 34 : P30 or address bit 8: in Port Mode: Port 3 Bit 0 in Bus Mode: CPU address bit 8 Pin 35 : P31 or address bit 9: in Port Mode: Port 3 Bit 1 in Bus Mode: CPU address bit 9 MICRONAS INTERMETALL Pin 27 : P21 or address bit 1: in Port Mode: Port 2 Bit 1 in Bus Mode: CPU address bit 1 Pin 28 : P22 or address bit 2: in Port Mode: Port 2 Bit 2 in Bus Mode: CPU address bit 2 Pin 29 : P23 or address bit 3: in Port Mode: Port 2 Bit 3 in Bus Mode: CPU address bit 3 Pin 30 : P24 or address bit 4: in Port Mode: Port 2 Bit 4 in Bus Mode: CPU address bit 4 Pin 31 : P25 or address bit 5: in Port Mode: Port 2 Bit 5 in Bus Mode: CPU address bit 5 Pin 20 : P12 or data bit 2: in Port Mode: Port 1 Bit 2 in Bus Mode: CPU data bit 2 Pin 21 : P13 or data bit 3: in Port Mode: Port 1 Bit 3 in Bus Mode: CPU data bit 3 Pin 22 : P14 or data bit 4: in Port Mode: Port 1 Bit 4 in Bus Mode: CPU data bit 4 Pin 23 : P15 or data bit 5: in Port Mode: Port 1 Bit 5 in Bus Mode: CPU data bit 5 Pin 24 : P16 or data bit 6: in Port Mode: Port 1 Bit 6 in Bus Mode: CPU data bit 6 Pin 25 : P17 or data bit 7: in Port Mode: Port 1 Bit 7 in Bus Mode: CPU data bit 7 Pin 26 : P20 or address bit 0: in Port Mode: Port 2 Bit 0 in Bus Mode: CPU address bit 0
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
Pin 36 : P32 or address bit 10: in Port Mode: Port 3 Bit 2 in Bus Mode: CPU address bit 10 Pin 37 : P33 or address bit 11: in Port Mode: Port 3 Bit 3 in Bus Mode: CPU address bit 11 Pin 38 : P34 or address bit 12: in Port Mode: Port 3 Bit 4 in Bus Mode: CPU address bit 12 Pin 39 : P35 or address bit 13: in Port Mode: Port 3 Bit 5 in Bus Mode: CPU address bit 13 Pin 40 : P36 or address bit 14: in Port Mode: Port 3 Bit 6 in Bus Mode: CPU address bit 14 Pin 41 : P37 or address bit 15: in Port Mode: Port 3 Bit 7 in Bus Mode: CPU address bit 15 Pin 42 : P50 or RDPort1\: in Port Mode: in Normal Mode: Port 5 Bit 0 (open drain output) in Special Mode: read port 1 (low active) in Bus Mode: in Normal Mode: Port 5 Bit 0 (open drain output) in Special Mode: read port 1 (low active) Pin 43 : P51 or WRPort1\: in Port Mode: in Normal Mode: Port 5 Bit 1 (open drain output) in Special Mode: write port 1 (low active) in Bus Mode: in Normal Mode: Port 5 Bit 1 (open drain output) in Special Mode: write port 1 (low active) Pin 44 : P52 or RDPort2\: in Port Mode: in Normal Mode: Port 5 Bit 2 (open drain output) in Special Mode: read port 2 (low active) in Bus Mode: in Normal Mode: Port 5 Bit 2 (open drain output) in Special Mode: read port 2 (low active) Pin 45 : P53 or WRPort2\: in Port Mode: in Normal Mode: Port 5 Bit 3 (open drain output) in Special Mode: write port 2 (low active) in Bus Mode: in Normal Mode: Port 5 Bit 3 (open drain output) in Special Mode: write port 2 (low active) Pin 46 : P54 or RDPort3\: in Port Mode: in Normal Mode: Port 5 Bit 4 (open drain output) in Special Mode: read port 3 (low active) in Bus Mode: in Normal Mode: Port 5 Bit 4 (open drain output) in Special Mode: read port 3 (low active) Pin 47 : P55 or WRPort3\: in Port Mode: in Normal Mode: Port 5 Bit 5 (open drain output) in Special Mode: write port 3 (low active) in Bus Mode: in Normal Mode: Port 5 Bit 5 (open drain output) in Special Mode: write port 3 (low active) Pin 48 : P70 or Memory Bank Address 0: in Port Mode: in Normal Mode: Port 7 Bit 0 in Special Mode: Memory Bank Address 0 in Bus Mode: in Normal Mode: Port 7 Bit 0 in Special Mode: Memory Bank Address 0 Pin 49 : P71 or Memory Bank Address 1: in Port Mode: in Normal Mode: Port 7 Bit 1 in Special Mode: Memory Bank Address 1 in Bus Mode: in Normal Mode: Port 7 Bit 1 in Special Mode: Memory Bank Address 1 Pin 50 : P72 or Memory Bank Address 2: in Port Mode: in Normal Mode: Port 7 Bit 2 in Special Mode: Memory Bank Address 2 in Bus Mode: in Normal Mode: Port 7 Bit 2 in Special Mode: Memory Bank Address 2 Pin 51 : P73 or Memory Bank Address 3: in Port Mode: in Normal Mode: Port 7 Bit 3 in Special Mode: Memory Bank Address 3 in Bus Mode: in Normal Mode: Port 7 Bit 3 in Special Mode: Memory Bank Address 3 Pin 52 : P74 or Memory Bank Address 4: in Port Mode: in Normal Mode: Port 7 Bit 4 in Special Mode: Memory Bank Address 4 in Bus Mode: in Normal Mode: Port 7 Bit 4 in Special Mode: Memory Bank Address 4
MICRONAS INTERMETALL
29
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
Pin 53 : P75 or Memory Bank Address 5: in Port Mode: in Normal Mode: Port 7 Bit 5 in Special Mode: Memory Bank Address 5 in Bus Mode: in Normal Mode: Port 7 Bit 5 in Special Mode: Memory Bank Address 5 Pin 54 : P76 or inverted CPU R/W\: in Port Mode: in Normal Mode: Port 7 Bit 6 in Special Mode: inverted CPU R/W\, i.e.: low active at read in Bus Mode: in Normal Mode: Port 7 Bit 6 in Special Mode: inverted CPU R/W\, i.e.: low active at read Pin 55 : P77 or Power-down Control: in Port Mode: in Normal Mode: Port 7 Bit 7 in Special Mode: Power-down Control External Memory (high active) in Bus Mode: in Normal Mode: Port 7 Bit 7 in Special Mode: Power-down Control External Memory (high active) Pin 56 : P80: Port 8 Bit 0 Pin 57 : P81: Port 8 Bit 1 Pin 58 : P82: Port 8 Bit 2 Pin 59 : P83: Port 8 Bit 3 Pin 60 : P87/INT: Port 8 Bit 7 and interrupt input (interrupt controller source 7) Pin 61 : P60: Port 6 Bit 0 Pin 62 : P61: Port 6 Bit 1 Pin 63 : P62: Port 6 Bit 2 Pin 64 : P63: Port 6 Bit 3 Pin 65 : P64: Port 6 Bit 4 Pin 66 : P65: Port 6 Bit 5 Pin 67 : P66: Port 6 Bit 6 Pin 68 : P67: Port 6 Bit 7
30
MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
4.5. Pin Circuits
fosc 4 3
VSUP
Fig. 4-6: X1, X2
13...41 in special mode: 42...60 GND Fig. 4-10: P1, P2, P3, Timer (1, 2, 3), IR (Input only), in special mode: P5, P7, P8
VSUP
VSUP
42...60 6 por, cls, watchdog Fig. 4-7: Reset GND Fig. 4-11: P5, P6, P7, P8 in port mode in port mode GND
VSUP
VSUP
17 7...12 RESET GND Fig. 4-8: IM bus Fig. 4-12: R/W, / P4, CCU 3001 GND
VSUP RESET
17 GND Fig. 4-9: R/W, CCU 3000
MICRONAS INTERMETALL
31
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
4.6. Electrical Characteristics All voltages refer to ground. 4.6.1. Absolute Maximum Ratings Symbol TA TS VSUP VI Parameter Ambient Operating Temperature Storage Temperature Supply Voltage Input Voltage Pin - - 1 4, 6, 16, 13 to 25, 42 to 68 - Min. 0 -40 -0.5 -0.3 V Max. 65 +125 6 VSUP+0.3 V Unit C C V -
Pmax
Maximum Power Dissipation
-
500
mW
The total sum of all the sink currents of all ports together must not exceed 80 mA Ioutlow and 280 mA - Iout high at any time. Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 4.6.2. Recommended Operating Conditions at TA = 0 C to 65C Symbol VSUP fCLK Parameter Supply Voltage Clock Frequency Pin 1 3, 4 Min. 4.75 0.5 Typ. - - Max. 5.25 8 Unit V MHz
4.6.3. Recommended Crystal Characteristics at CXTAL1 = CXTAL2 = 22 pF; Cstray 2 pF; CL 13 pF Symbol TA fp Rr C0 C1 P fp / fH Parameter Ambient Operating Temperature Parallel Resonance Frequency @ CL = 13 pF Series Resistance Shunt Capacitance Motional Capacitance Rated Drive Level Spurious Frequency Attenuation Min. -20 - - - - - 20 Typ. - 4-8 - - - 0.02 - Max. +85 - 40 [8MHz] 150 [4 MHz] 7.0 20 - - Unit C MHz pF fF mW dB
32
MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
4.6.4. DC Characteristics at TA = 0 C to 65C, VSUP = 5V, fCLK = 8 MHz
Symbol ISUP CCU 3000, CCU 3000-I ISUP CCU 3001 CCU 3001-I VILH
Parameter Supply Current (no external load)
Pin No. 1
Min. -
Typ. 8/16
Max. 15/30
Unit mA
Comment @ 4/8 MHz
Supply Current (no external load)
1
-
14/28
20/40
mA
@ 4/8 MHz
Input Low to High Trigger Level
4,6, 7-12, 13-25, 42-68
0.38* VSUP
2,05
0.56* VSUP
V
Schmitt-Trigger Inputs
VIHL
Input High to Low Trigger Level
0.2* VSUP 4,6, 7-25, 42-68 13-15 17-41 0.1* VSUP
1.15
0.29* VSUP 0.27* VSUP
V
Schmitt-Trigger Inputs
VIHYST
Input Hysteresis
0.9
V
Schmitt-Trigger Inputs
VBOH VBOL IBOH IBOL IP5OL IP6OL IP7OL IP8OL IOHL IP5P7OH VP5P7OH VOL VOL VStby IStby VPow on
Bus Ports and Timer Output High Voltage Bus Ports and Timer Output Low Voltage Bus Ports and Timer Output High Current Bus Ports and Timer Output Low Current P5 Output Low Current P6 Output Low Current P7 Output Low Current P8 Output Low Current Output Leakage Current
2.8
-
-
V
-
-
0.4
V
13-151 7-41
-
-
2
mA
-
-
5
mA
42-47 61-68 48-55 56-60 42-60
- - - - -
- - - - -
5 25 5 5 1
mA mA mA mA A
Output High Current Special Mode, P5 to P7 Output High Voltage Special Mode, P5 to P7 Output Low Voltage at IOL = 5 mA Output Low Voltage at IOL = 25 mA Stand-by Voltage RAM Stand-by Current RAM Power-on Voltage
42-55
-
-
2
mA
42-55
2.8
-
-
V
42-60
-
-
0.4
V
61-68
-
-
0.55
V
5 5 1
3 - 4.2
- - -
- 1 4.75
V A V @ VDD = 0 V, VStby = 5V
Bus Ports: P1, P2, P3, P4.
MICRONAS INTERMETALL
33
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
4.6.5. Using external devices To avoid collision on the data bus during direction changes, the CCU data bus out buffers (active during PHI2 = `1' only) are disabled before the address, the R/W and the R/W line changes (tDHW t tAH). This guarantees that no collision happens on the bus if the output drives of the external devices (ROM, RAM, Ports) are controlled with the R/W or R/W signal and a read cycle follows a write cycle. Important: In a write cycle the data-out drivers of the CCU set up the data bus lines. Then they leave these lines so that no drivers are active on the data bus. A few ns later the R/W or the P5 select signal latch the data into the external device (Port out or Write into RAM). The same signal is used to enable the output drivers of external devices for reading so that another few ns later they drive the bus. The DATA BUS is used as DATA MEMORY for a few ns. This is the only way to make sure that, independent from the loads on the CCU address, data and control lines collisions are avoided and a maximum of access time is available for the memory. IF YOU WANT TO WRITE TO EXTERNAL DEVICES THE DATA BUS MUST BE IN THE TRISTATE MODE DURING WRITE OPERATIONS OF THE CCU. No pullup or pull-down resistors are allowed. Even in a good layout the capacitive load on the data bus is approx. 20 pF (2* pin capacity and layout). Even in the worst case of a 1 M leakage the time constant is approx. 20 s. The max. time between disabling the bus drivers and the rising edge of R/W is 20 ns.
4.6.6. AC Characteristics at TA = 0 C to 65C, VSUP = 5 V, fCLK = 8 MHz, Cl = 0 pF External Loads: add 0.75 ns/pF for controller output lines Symbol tcyc tPWL tAH tADS tDSR tMDS tDHW tDHR tRWH tWRH tP5S tX12 t2X2 Parameter Cycle Time (Processor) Pulse Width Low Address Hold Time Address Setup Time Read Data Setup Time Read Write Data Delay Write Data Hold Time Read Data Hold Time Read/Write Hold Time Read/Write Hold Time (P76 special mode) Delay P1 to P3 Select Lines on P5 Delay X1 to internal2 Delay 2 internal to X2 17 17 42-47 4 3 18-25 Pin 3 3 26-41 Min. 125 60 10 15 20 10 9 10 10 13 12 7 5 Max. 2000 1000 22 34 - 29 16 - 24 34 26 15 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
34
MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
X1 2 internal
tX12 t PWL
t cyc
t ADS t AH A0...A15 t ACC t DHR READ DATA t DSR READ DATA
t DHW WRITE DATA t RWH R/W WR PORT 1 to 3 RD PORT 1 to 3 SELECT LINES
t MDS WRITE DATA
tP5S Fig. 4-13: AC timing
tP5S
MICRONAS INTERMETALL
35
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
4.6.7. IM Bus Waveforms
H Ident L H Clock L H Data L LSB Address MSB LSB Data MSB 1 2 3 4 5 6 7 8 9 10 11 12 13 16 or 24
A Section A
B Section B
C Section C
tIM10
H Ident L tIM1 tIM2 H Clock L tIM7 H Data L tIM8 tIM9 tIM3 tIM4 tIM5 tIM6
Address LSB
Address MSB
Data MSB
Fig. 4-14: IM bus waveforms 4.6.8. Description of the IM Bus The INTERMETALL Bus (IM bus for short) was designed to control the DIGIT 2000 ICs by the CCU Central Control Unit. Via this bus the CCU can write data to the ICs or read data from them. This means that the CCU acts as a master, whereas all controlled ICs have purely slave status. The IM bus consists of three lines for the signals Ident (ID), Clock (DL) and Data (D). The clock frequency range is 50 Hz to 1 MHz. Ident and clock are unidirectional from the CCU to the slave ICs, Data is bidirectional. Bidirectionality is achieved by using open-drain outputs. The 2.5 to 1 kOhm pull-up resistor common to all outputs must be connected externally. The timing of a complete IM bus transaction is shown in Fig. 4-14. In the non-operative state the signals of all three bus lines are High. To start a transaction the CCU sets the ID signal to Low level, indicating an address transmission, and sets the CL signal to Low level as well 36 as to switch the first bit on the Data line. Then eight address bits are transmitted, beginning with the the LSB. Data takeover in the slave ICs occurs at the positive edge of the clock signal. At the end of the address byte the ID signal switches to High, initiating the address comparison in the slave circuits. In the addressed slave the IM bus interface switches over to Data read or write, because these functions are correlated to the address. Also controlled by the address the CCU now transmits eight or sixteen clock pulses, and accordingly one or two bytes of data are written into the addressed IC or read out from it, beginning with the LSB. The completion of the bus transaction is signalled by a short Low state pulse of the ID signal. This initiates the storing of the transferred data. For future software compatibility, the CCU must write a zero into all bits not currently used. When reading undefined or unused bits, the CCU must adopt "don't care" behavior. MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
4.6.9. Recommended Operating Conditions of IM Bus
Symbol VIML VIMH Rext IIMOL fI tIM1 tIM2 tIM3 tIM4 tIM5 tIM6 tIM7 tIM8 tIM9 tIM10
Parameter IM bus Low Voltage IM bus High Voltage External Pull-Up Resistor IM bus Output Low Current I IM bus Clock Frequency I Clock Delay Time after IM bus Ident I Clock Low Pulse Time I Clock High Pulse Time I Clock Setup Time before Ident High I Clock Hold Time after Ident High I Clock Setup Time before Ident End-Pulse IM bus Data Delay Time after I Clock IM bus Data Setup Time before I Clock IM bus Data Hold Time after I Clock IM bus Ident End-Pulse Low Time
Pin No. Data 7, 7 10
Min. - 2.4 1 -
Typ. - - - - - - - - 0.5 tIM3 0.5 tIM3 tIM2 +tIM3 - - - tIM2 +tIM3
Max. 0.8 - 2.5 5 1000 - - - - - - - - - -
Unit V V k mA kHz - ns ns ns ns s ns ns ns s
Clock 9, 9 12
0.05 >0 500 500 >0 250 1 >0
Clock, Data 7, 9 10, 7 9, 10 12 Ident 8, 11
>0 >0 1
MICRONAS INTERMETALL
37
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
4.6.10. Registers
0200H Bit 7 to 3 2 1 0
System Clock Prescaler Reset 0 1 0 0 Read x x x x Divisor value -1 Write
0201H Bit 7 6 5 4 3 2 1 0
Control Register Reset copy from addr. FFF9H x external bus: `1' = bus on ports 0, 1, 2 disabled R/W signal / Port4: `0' = R/W, `1' = P40 internal ROM: `1' = internal ROM enabled internal RAM: `1' = internal RAM enabled internal CPU: `1' = internal CPU enabled x Read x Write no function - set to `1' (to keep compatibility) no function - set to `1' (to keep compatibility) no function - set to `1' (to keep compatibility) Bus disable: `1" = disable bus on ports 0, 1, 2 R/W signal / Port4: `0' = R/W, `1' = P40 ROM enable: `1' = enable internal ROM RAM enable: `1' = enable internal RAM CPU enable: `1' = enable internal CPU
0202H Bit 7 6 5 4 3 2 1 0
Watchdog Control and Status Reset x x x x x x x 1/0 Read x x x x x x x `0': last RESET was generated by watchdog Write Watchdog time value = ( fsystem 65536 * -1 = n Twd = (n+1) * 65536 fsystem (don't use setting n<2!!) with fsystem = 4 MHz: n = nmin = 2 Twdmin = 49.152 ms n = nmax = 255 Twdmax = 4.17792 s min. n = 1 min. T wd =16.384 ms Twd )
38
MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
0203H Bit 7 to 0 Port 1 Data Register Reset 0 Read Port 1 Data Write Port 1 Data
0204H Bit 7 to 0
Port 1 Direction Register Reset 1 Read x Write `1' = input, `0' = output mode
0205H Bit 7 to 0
Port 2 Data Register Reset 0 Read Port 2 Data Write Port 2 Data
0206H Bit 7 to 0
Port 2 Direction Register Reset 1 Read x Write `1' = input, `0' = output mode
0207H Bit 7 to 0
Port 3 Data Register Reset 0 Read Port 3 Data Write Port 3 Data
0208H Bit 7 to 0
Port 3 Direction Register Reset 1 Read x Write `1' = input, `0' = output mode
0209H Bit 7 to 1 0
Port 4 Data Register Reset x 0 Read x Port 4 Data (bit 0 only) Write x Port 4 data (bit 0, only)
020AH Bit 7 to 6 5 to 0
Port 5 Mode Reset x x Read x Port 4 Data (bit 0 only) Write x `1' = port select mode, `0' = port mode
MICRONAS INTERMETALL
39
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
020BH Bit 7 to 6 5 to 0 Port 5 Direction Register Reset x 1 Read x x Write x `1' = input, `0' = output mode
020CH Bit 7 to 6 5 4 3 2 1 0
Port 5 Data Register Reset x 0 0 0 0 0 0 Read x Data bit 5 Data bit 4 Data bit 3 Data bit 2 Data bit 1 Data bit 0 Write x Data bit 5 Data bit 4 Data bit 3 Data bit 2 Data bit 1 Data bit 0
020DH Bit 7 to 3 2 1 0
IR Input Reset x x x x Read x IR-pin logic level `1' if a falling edge occurred since last read, else `0' `1' if a rising edge occurred since last read, else `0' Write x x x x
020FH Bit 7 6 5 4 3 2 1 0
Port 7 Mode Register Reset 0 0 0 0 0 0 0 0 Read x x x x x x x x Write `0' = port mode, `1' = power down control for external memory `0' = port mode, `1' = \R/W output `0' = port mode, `1' = banking addr. bit 5 `0' = port mode, `1' = banking addr. bit 4 `0' = port mode, `1' = banking addr. bit 3 `0' = port mode, `1' = banking addr. bit 2 `0' = port mode, `1' = banking addr. bit 1 `0' = port mode, `1' = banking addr. bit 0
40
MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
0210H Bit 7 to 4 3 2 1 0 IM Bus 1 Control and Status Register Reset x 0 0 0 0 Read x `1' = 1 byte received in slave register 3 (IM bus address 4) `1' = 1 byte received in slave register 2 (IM bus address 3) `1' = 1 byte received in slave register 1 (IM bus address 2) `1' = IM bus (master) busy Write x `1' = read word via IM bus (master) `1' = read byte via IM bus (master) `1' = write word via IM bus (master) `1' = write byte via IM bus (master) (bits 0 to 3: `0000'= reset IM bus ) interface)
0211H Bit 7 to 6 5 4 3 2 1 0
IM Bus 1 Data Transfer Rate Register Reset x x x x x x x Read x x x x x x x Write x transfer rate bit 5 transfer rate bit 4 transfer rate bit 3 transfer rate bit 2 transfer rate bit 1 transfer rate bit 0
0213H Bit 7 6 5 4 3 2 1 0
IM Bus 1 Master Address Register Reset x x x x x x x x Read x x x x x x x x Write IM bus address bit 7 IM bus address bit 6 IM bus address bit 5 IM bus address bit 4 IM bus address bit 3 IM bus address bit 2 IM bus address bit 1 IM bus address bit 0
MICRONAS INTERMETALL
41
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
0214H Bit 7 6 5 4 3 2 1 0 IM Bus 1 Master Data Register, Low Byte Reset x x x x x x x x Read IM bus data bit 7 IM bus data bit 6 IM bus data bit 5 IM bus data bit 4 IM bus data bit 3 IM bus data bit 2 IM bus data bit 1 IM bus data bit 0 (LSB) Write IM bus data bit 7 IM bus data bit 6 IM bus data bit 5 IM bus data bit 4 IM bus data bit 3 IM bus data bit 2 IM bus data bit 1 IM bus data bit 0 (LSB)
0215H Bit 7 6 5 4 3 2 1 0
IM Bus 1 Master Data Register, High Byte Reset x x x x x x x x Read IM bus data bit 15 (MSB) IM bus data bit 14 IM bus data bit 13 IM bus data bit 12 IM bus data bit 11 IM bus data bit 10 IM bus data bit 9 IM bus data bit 8 Write IM bus data bit 15 (MSB) IM bus data bit 14 IM bus data bit 13 IM bus data bit 12 IM bus data bit 11 IM bus data bit 10 IM bus data bit 9 IM bus data bit 8
0216H Bit 7 6 5 4 3 2 1 0
IM Bus 1 Slave 1 Register (IM Bus Address 2) Reset x x x x x x x x Read IM bus data, bit 7 IM bus data, bit 6 IM bus data, bit 5 IM bus data, bit 4 IM bus data, bit 3 IM bus data, bit 2 IM bus data, bit 1 IM bus data, bit 0 Write x x x x x x x x
42
MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
0218H Bit 7 6 5 4 3 2 1 0 IM Bus 1 Slave 2 Register (IM Bus Address 3) Reset x x x x x x x x Read IM bus data, bit 7 IM bus data, bit 6 IM bus data, bit 5 IM bus data, bit 4 IM bus data, bit 3 IM bus data, bit 2 IM bus data, bit 1 IM bus data, bit 0 Write x x x x x x x x
021AH Bit 7 6 5 4 3 2 1 0
IM Bus 1 Slave 3 Register (IM Bus Address 4) Reset x x x x x x x x Read IM bus data, bit 7 IM bus data, bit 6 IM bus data, bit 5 IM bus data, bit 4 IM bus data, bit 3 IM bus data, bit 2 IM bus data, bit 1 IM bus data, bit 0 Write x x x x x x x x
021CH Bit 7 to 5 4 3 2 1 0
Interrupt Controller Control Register Reset x 0 1 1 1 0 Read x x x x x x Write x `0' = reset interrupt controller `0' = disable after interrupt `0' = disable interrupts `0' = allow next interrupt `0' = clear all requests
MICRONAS INTERMETALL
43
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
021DH Bit 7 6 5 4 3 2 1 0 Interrupt Controller Return Register Reset x x x x x x x x Read x x x x x x x x Write x x x x x x x x The `write' to this register is the handshake for the interrupt controller that the current interrupt request is served.
021EH Bit 7 6 5 4 3 2 1 0
Interrupt Priorities: Source 1 = Timer 2 and Source 0 = Timer 1 Reset 0 0 0 0 0 0 0 0 Read x x x x x x x x Write xxxx xxxx
Interrupt priority value for source 1 = timer 2 values 0 to 7: 0 = interrupt disabled 1 = lowest priority 7 = highest priority Interrupt priority value for source 0 = timer 1 values 0 to 7: 0 = interrupt disabled 1 = lowest priority 7 = highest priority
00001111 00110011 0 1 01 0
off low
101
high
xxxx
xxxx
00001111 00110011 0 1 01 0 101
021FH Bit 7 6 5 4 3 2 1 0
Interrupt Priorities: Source 3 = IM Bus 1 Master and Source 2 = Timer 3 Reset 0 0 0 0 0 0 0 0 Read x x x x x x x x Write xxxx xxxx
Interrupt priority value for source 3 = IM bus 1 Master values 0 to 7: 0 = interrupt disabled 1 = lowest priority 7 = highest priority Interrupt priority value for source 2 = timer 3 (1 ms) values 0 to 7: 0 = interrupt disabled 1 = lowest priority 7 = highest priority
00001111 00110011 0 1 01 0
off low
101
high
xxxx
xxxx
00001111 00110011 0 1 01 0 101
44
MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
0220H Bit 7 6 5 4 3 2 1 0 Interrupt Priorities: Source 5 = IM Bus 2 Master and Source 4 = IM bus 1 Slave Reset 0 0 0 0 0 0 0 0 Read x x x x x x x x Write xxxx xxxx
Interrupt priority value for source 5 = IM bus 2 Master values 0 to 7: 0 = interrupt disabled 1 = lowest priority 7 = highest priority
00001111 00110011
0 1 01 0 10 1 off low high Interrupt priority x x x x x x x x value for source 4 00001111 00110011 0 1 01 0 101
=IM bus 1 slave values 0 to 7: 0 = interrupt disabled 1 = lowest priority 7 = highest priority
0221H Bit 7 6 5 4 3 2 1 0
Interrupt Priorities: Source 7 = P87 and Source 6 = IM bus 2 Slave Reset 0 0 0 0 0 0 0 0 Read x x x x x x x x Write xxxx xxxx
Interrupt priority value for source 7 = P87 values 0 to 7: 0 = interrupt disabled 1 = lowest priority 7 = highest priority
00001111 00110011
0 1 01 0 10 1 off low high Interrupt priority x x x x x x x x value for source 4 00001111 00110011 0 1 01 0 101
=IM bus 2 slave values 0 to 7: 0 = interrupt disabled 1 = lowest priority 7 = highest priority
0222H Bit 7 6 5 4 3 2 1 0
Timer 1 Control Register 1 Reset x x x x x x x x Read x x x x x x x x Write `1' = second serial input level enabled clock select, bit 1: clock select, bit 0: counter stop: `00' = pin, `01' = fosc
`10' = PHI2, `11' = no clock `1' = carry out accu
`0' = disabled,
start condition, bit 1: `00' = none (always active) start condition, bit 0: `01' = edge, `10' = pin, `11' = \ pin `1' = half load enabled active edge selection: `0' = rising, `1' = falling
MICRONAS INTERMETALL
45
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
0223H Bit 7 6 5 4 3 2 1 0 Timer 1 Control Register 2 Reset x x x x x x x x Read x x x x x x x x Write pin output mode, bit 1: 00 = disabled, 01 = serial out pin output mode, bit 0: 10 = PWM, 11 = carry accu D read latch, bit 2: 000 = disabled, 001 = carry accu C read latch, bit 1: `010' = carry accu D, `011' pin read latch, bit 0: `100' = \pin, `101' = prescaler output, `110' = prescaler input, `111' = undefined accu clock, bit 1: `00' = presc. input, `01' = pre.output accu clock, bit 0: `10' = pin, `11' = \ pin `1' = use accu c with accu d as long one (16bit accu)
0224H Bit 7 6 5 4 3 2 1 0
Timer 1 Control Register 3 Reset x x x x x x x x Read x x x x x x x x Write interrupt event, bit 2:`000' = none, `001' = pin interrupt event, bit 1:`010' = \pin, `011' = carry accu C, interrupt event, bit 0:`100' = carry accu D, `101', `110', `111' = undefined load event, bit 1: `00': `00' = none, `01' = carry accu C, load event, bit 0: `10 = carry accu D, `11' = reg. load accu C input: `0' = bus register, `1' = -1 accu D input: `0' = bus register, `1' = -1 serial mode enable: `0' = disable, `1' = enable
0225H Bit 7 6 5 4 3 2 1 0
Timer 1 Prescaler Low Byte Reset x x x x x x x x Read x x x x x x x x Write scaler value bit 7 scaler value bit 6 scaler value bit 5 scaler value bit 4 scaler value bit 3 scaler value bit 2 scaler value bit 1 scaler value bit 0 (LSB)
46
MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
0226H Bit 7 6 5 4 3 2 1 0 Timer 1 Prescaler High Byte Reset x x x x x x x x Read x x x x x x x x Write scaler value bit 15 (MSB) scaler value bit 14 scaler value bit 13 scaler value bit 12 scaler value bit 11 scaler value bit 10 scaler value bit 9 scaler value bit 8
0228H Bit 7 6 5 4 3 2 1 0
Timer 1 Accu Low Byte (Accu C) Reset x x x x x x x x Read x x x x x x x x Write accu bit 7 accu bit 6 accu bit 5 accu bit 4 accu bit 3 accu bit 2 accu bit 1 accu bit 0 (LSB)
0229H Bit 7 6 5 4 3 2 1 0
Timer 1 Accu High Byte (Accu D) Reset x x x x x x x x Read x x x x x x x x Write accu bit 15 (MSB) accu bit 14 accu bit 13 accu bit 12 accu bit 11 accu bit 10 accu bit 9 accu bit 8
MICRONAS INTERMETALL
47
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
022AH Bit 7 6 5 4 3 2 1 0 Timer 1 Adder Low Byte Reset x x x x x x x x Read adder bit 7 adder bit 6 adder bit 5 adder bit 4 adder bit 3 adder bit 2 adder bit 1 adder bit 0 (LSB) Write adder bit 7 adder bit 6 adder bit 5 adder bit 4 adder bit 3 adder bit 2 adder bit 1 adder bit 0 (LSB)
022BH Bit 7 6 5 4 3 2 1 0
Timer 1 Adder High Byte Reset x x x x x x x x Read adder bit 15 (MSB) adder bit 14 adder bit 13 adder bit 12 adder bit 11 adder bit 10 adder bit 9 adder bit 8 Write adder bit 15 (MSB) adder bit 14 adder bit 13 adder bit 12 adder bit 11 adder bit 10 adder bit 9 adder bit 8
022CH Bit 7 6 5 4 3 2 1 0
Timer 2 Control Register 1 Reset x x x x x x x x Read x x x x x x x x Write `1' = second serial input level enabled clock select, bit 1: `00' = pin, `01' = fosc., clock select, bit 0: `10' = PHI2, `11' = no clock counter stop: `0' = disabled , `1' = carry out accu start condition, bit 1: `00'= none (always active), start condition, bit 0: `01' = edge, `10' = pin, `11' =\pin `1' = half load enabled active edge selection: `0' = rising `1' = falling
48
MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
022DH Bit 7 6 5 4 3 2 1 0 Timer 2 Control Register 2 Reset x x x x x x x x Read x x x x x x x x Write pin output mode, bit 1: `00' = disabled, `01' = serial out, pin output mode, bit 0: `10' = PWM, `11' = carry accu D read latch, bit 2: `000' = disabled, `001' = carry accu C read latch, bit 1: `010' = carry accu D, `011' pin read latch, bit 0: `100' = \pin, `101' = prescaler output, `110' = presc. input, `111' = undefined accu clock, bit 1: `00' = presc. input, `01' = presc. output accu clock, bit 0: `10' = pin, `11' = \pin `1' = use accu C with accu D as long one (16-bit accu)
022EH Bit 7 6 5 4 3 2 1 0
Timer 2 Control Register 3 Reset x x x x x x x x Read x x x x x x x x Write interrupt event, bit 2: `000' = none, `001' = pin interrupt event, bit 1: `010' = \pin, `011' = carry accu C interrupt event, bit 0: `100' = carry accu D, `101', `110', `111' = undefined load event, bit 1: `00' = none, `01' = carry accu C, load event, bit 0: `10' = carry accu D, `11' = register load accu C input: `0' = bus register, `1' = -1 accu D input: `0' = bus register, `1' = -1 serial mode enable: `0' = disable, `1' = enable
MICRONAS INTERMETALL
49
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
022FH Bit 7 6 5 4 3 2 1 0 Timer 2 Prescaler Low Byte Reset x x x x x x x x Read x x x x x x x x Write scaler value bit 7 scaler value bit 6 scaler value bit 5 scaler value bit 4 scaler value bit 3 scaler value bit 2 scaler value bit 1 scaler value bit 0 (LSB)
0230H Bit 7 6 5 4 3 2 1 0
Timer 2 Prescaler High Byte Reset x x x x x x x x Read x x x x x x x x Write scaler value bit 15 (MSB) scaler value bit 14 scaler value bit 13 scaler value bit 12 scaler value bit 11 scaler value bit 10 scaler value bit 9 scaler value bit 8
0232H Bit 7 6 5 4 3 2 1 0
Timer 2 Accu Low Byte (Accu C) Reset x x x x x x x x Read x x x x x x x x Write accu bit 7 accu bit 6 accu bit 5 accu bit 4 accu bit 3 accu bit 2 accu bit 1 accu bit 0 (LSB)
50
MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
0233H Bit 7 6 5 4 3 2 1 0 Timer 2 Accu High Byte (Accu D) Reset x x x x x x x x Read x x x x x x x x Write accu bit 15 (MSB) accu bit 14 accu bit 13 accu bit 12 accu bit 11 accu bit 10 accu bit 9 accu bit 8
0234H Bit 7 6 5 4 3 2 1 0
Timer 2 Adder Low Byte Reset x x x x x x x x Read adder bit 7 adder bit 6 adder bit 5 adder bit 4 adder bit 3 adder bit 2 adder bit 1 adder bit 0 (LSB) Write adder bit 7 adder bit 6 adder bit 5 adder bit 4 adder bit 3 adder bit 2 adder bit 1 adder bit 0 (LSB)
0235H Bit 7 6 5 4 3 2 1 0
Timer 2 Adder High Byte Reset x x x x x x x x Read adder bit 15 (MSB) adder bit 14 adder bit 13 adder bit 12 adder bit 11 adder bit 10 adder bit 9 adder bit 8 Write adder bit 15 (MSB) adder bit 14 adder bit 13 adder bit 12 adder bit 11 adder bit 10 adder bit 9 adder bit 8
MICRONAS INTERMETALL
51
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
0236H Bit 7 6 5 4 3 2 1 0 Timer 3 Control Register 1 Reset x x x x x x x x Read x x x x x x x x Write `1' = second serial input level enabled clock select, bit 1: `00' = pin, `01' = fosc., clock select, bit 0: `10' = PHI2, `11' = no clock counter stop: `0' = disabled , `1' = carry out accu start condition, bit 1: `00'= none (always active), start condition, bit 0: `01' = edge, `10' = pin, `11' =\pin `1' = half load enabled active edge selection: `0' = rising, `1' = falling
0237H Bit 7 6 5 4 3 2 1 0
Timer 3 Control Register 2 Reset x x x x x x x x Read x x x x x x x x Write pin output mode, bit 1: 00 = disabled, 01 = serial out pin output mode, bit 0: 10 = PWM, 11 = carry accu D read latch, bit 2: 000 = disabled, 001 = carry accu C read latch, bit 1: `010' = carry accu D, `011' pin read latch, bit 0: `100' = \pin, `101' = prescaler output, `110' = presc. input, `111' = undefined accu clock, bit 1: `00' = presc. input, `01' = presc. output accu clock, bit 0: `10' = pin, `11' = \pin 1 = use acc. C with acc. D as long one (16-bit acc.)
0238H Bit 7 6 5 4 3 2 1 0
Timer 3 Control Register 3 Reset x x x x x x x x Read x x x x x x x x Write interrupt event, bit 2: `000' = none, `001' = pin interrupt event, bit 1: `010' = \pin, 011 = carry accu C interrupt event, bit 0: `100' = carry accu D, `101', `110', `111' = undefined load event, bit 1: `00' = none, `01' = carry accu C, load event, bit 0: 10 = carry accu D, 11 = regist. load accu C input: `0' = bus register, `1' = -1 accu D input: `0' = bus register, `1' = -1 serial mode enable: `0' = disable, `1' = enable
52
MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
0239H Bit 7 6 5 4 3 2 1 0 Timer 3 Prescaler Low Byte Reset x x x x x x x x Read x x x x x x x x Write scaler value bit 7 scaler value bit 6 scaler value bit 5 scaler value bit 4 scaler value bit 3 scaler value bit 2 scaler value bit 1 scaler value bit 0 (LSB)
023AH Bit 7 6 5 4 3 2 1 0
Timer 3 Prescaler High Byte Reset x x x x x x x x Read x x x x x x x x Write scaler value bit 15 (MSB) scaler value bit 14 scaler value bit 13 scaler value bit 12 scaler value bit 11 scaler value bit 10 scaler value bit 9 scaler value bit 8
023CH Bit 7 6 5 4 3 2 1 0
Timer 3 Accu Low Byte (Accu C) Reset x x x x x x x x Read x x x x x x x x Write accu bit 7 accu bit 6 accu bit 5 accu bit 4 accu bit 3 accu bit 2 accu bit 1 accu bit 0 (LSB)
MICRONAS INTERMETALL
53
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
023DH Bit 7 6 5 4 3 2 1 0 Timer 3 Accu High Byte (Accu D) Reset x x x x x x x x Read x x x x x x x x Write accu bit 15 (MSB) accu bit 14 accu bit 13 accu bit 12 accu bit 11 accu bit 10 accu bit 9 accu bit 8
023EH Bit 7 6 5 4 3 2 1 0
Timer 3 Adder Low Byte Reset x x x x x x x x Read adder bit 7 adder bit 6 adder bit 5 adder bit 4 adder bit 3 adder bit 2 adder bit 1 adder bit 0 (LSB) Write adder bit 7 adder bit 6 adder bit 5 adder bit 4 adder bit 3 adder bit 2 adder bit 1 adder bit 0 (LSB)
023FH Bit 7 6 5 4 3 2 1 0
Timer 3 Adder High Byte Reset x x x x x x x x Read adder bit 15 (MSB) adder bit 14 adder bit 13 adder bit 12 adder bit 11 adder bit 10 adder bit 9 adder bit 8 Write adder bit 15 (MSB) adder bit 14 adder bit 13 adder bit 12 adder bit 11 adder bit 10 adder bit 9 adder bit 8
54
MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
0240H Bit 7 to 0 Port 6 Data Register Reset 0 Read Port 6 Data Write Port 6 Data
0241H Bit 7 to 0
Port 6 Direction Register Reset 1 Read x Write `1' = input, `0' = output mode
0242H Bit 7 to 0
Port 7 Data Register Reset 0 Read Port 7 Data Write Port 7 Data
0243H Bit 7 to 0
Port 7 Direction Register Reset 1 Read x Write `1' = input, `0' = output mode
0244H Bit 7 6 to 4 3 2 1 0
Port 8 Data Register Reset 0 x 0 0 0 0 Read Data bit 7 x Data bit 3 Data bit 2 Data bit 1 Data bit 0 Write Data bit 7 x Data bit 3 Data bit 2 Data bit 1 Data bit 0
MICRONAS INTERMETALL
55
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
0245H Bit 7 6 5 4 3 2 1 0 Port 8 Direction Register Reset 1 x x x 1 1 1 1 Read x x x x x x x x Write `1' = input, `0' = output mode x x x `1' = input, `0' = output mode `1' = input, `0' = output mode `1' = input, `0' = output mode `1' = input, `0' = output mode
0246H Bit 7 to 4 3 2 1 0
IM Bus 2 Control and Status Register Reset x 0 0 0 0 Read x `1' = 1 byte received in slave register 3 (IM bus address 4) `1' = 1 byte received in slave register 2 (IM bus address 3) `1' = 1 byte received in slave register 1 (IM bus address 2) `1' = IM bus (master) busy Write x `1' = read word via IM bus (master) `1' = read byte via IM bus (master) `1' = write word via IM bus (master) `1' = write byte via IM bus (master) (bits 0 ... 3: `0000'= reset IM bus interface) )
0247H Bit 7 to 6 5 4 3 2 1 0
IM Bus 2 Data Transfer Rate Register Reset x x x x x x x Read x x x x x x x Write x transfer rate bit 5 transfer rate bit 4 transfer rate bit 3 transfer rate bit 2 transfer rate bit 1 transfer rate bit 0
56
MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
0249H Bit 7 6 5 4 3 2 1 0 IM Bus 2 Master Address Register Reset x x x x x x x x Read x x x x x x x x Write IM bus address bit 7 IM bus address bit 6 IM bus address bit 5 IM bus address bit 4 IM bus address bit 3 IM bus address bit 2 IM bus address bit 1 IM bus address bit 0
024AH Bit 7 6 5 4 3 2 1 0
IM Bus 2 Master Data Register, Low Byte Reset x x x x x x x x Read IM bus data, low byte, bit 7 IM bus data, low byte, bit 6 IM bus data, low byte, bit 5 IM bus data, low byte, bit 4 IM bus data, low byte, bit 3 IM bus data, low byte, bit 2 IM bus data, low byte, bit 1 IM bus data, low byte, bit 0 Write IM bus data, low byte, bit 7 IM bus data, low byte, bit 6 IM bus data, low byte, bit 5 IM bus data, low byte, bit 4 IM bus data, low byte, bit 3 IM bus data, low byte, bit 2 IM bus data, low byte, bit 1 IM bus data, low byte, bit 0
024BH Bit 7 6 5 4 3 2 1 0
IM Bus 2 Master Data Register, High Byte Reset x x x x x x x x Read IM bus data, high byte, bit 7 IM bus data, high byte, bit 6 IM bus data, high byte, bit 5 IM bus data, high byte, bit 4 IM bus data, high byte, bit 3 IM bus data, high byte, bit 2 IM bus data, high byte, bit 1 IM bus data, high byte, bit 0 Write IM bus data, high byte, bit 7 IM bus data, high byte, bit 6 IM bus data, high byte, bit 5 IM bus data, high byte, bit 4 IM bus data, high byte, bit 3 IM bus data, high byte, bit 2 IM bus data, high byte, bit 1 IM bus data, high byte, bit 0
MICRONAS INTERMETALL
57
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
024CH Bit 7 6 5 4 3 2 1 0 IM Bus 2 Slave 1 Register (IM Bus Address 2) Reset x x x x x x x x Read IM bus data, bit 7 IM bus data, bit 6 IM bus data, bit 5 IM bus data, bit 4 IM bus data, bit 3 IM bus data, bit 2 IM bus data, bit 1 IM bus data, bit 0 Write x x x x x x x x
024EH Bit 7 6 5 4 3 2 1 0
IM Bus 2 Slave 2 Register (IM Bus Address 3) Reset x x x x x x x x Read IM bus data, bit 7 IM bus data, bit 6 IM bus data, bit 5 IM bus data, bit 4 IM bus data, bit 3 IM bus data, bit 2 IM bus data, bit 1 IM bus data, bit 0 Write x x x x x x x x
0250H Bit 7 6 5 4 3 2 1 0
IM Bus 2 Slave 3 Register (IM Bus Address 4) Reset x x x x x x x x Read IM bus data, bit 7 IM bus data, bit 6 IM bus data, bit 5 IM bus data, bit 4 IM bus data, bit 3 IM bus data, bit 2 IM bus data, bit 1 IM bus data, bit 0 Write x x x x x x x x
58
MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
5. Index Interrupt, 4, 5, 10 Interrupt controller, 4, 5, 10, 11, 21, 22, 66 IR-input, 21, 22, 66 IR-input, 4 Access time, 5 Accu, 16, 17, 18, 22, 66 Accumulator, 14, 17 Adder, 16, 22, 66 Arithmetic unit, 14 Asynchronous interface, 14
A
L
Lines, 4, 5, 6, 12, 34, 36, 65
M
Mask-programmed, 5 Master, 12, 22, 36, 66 Master address, 12, 22 Master data, 12, 22 Mode register, 22, 66 Multimaster ability, 12
B
Bus external bit, 8
C
Clock, 4, 5, 10, 17, 21, 22, 32, 37, 66 Clock supervision, 4, 21 Control byte, 10, 22, 66 Control register, 5, 8, 12, 13 Counter, 14, 16
O
Open drain outputs, 5 OSC, 5 Oscillator, 5, 8
D
Data transfer rate, 22 Direction register, 5, 6, 22, 66
P
P4, 5, 8, 31, 33, 34 Page 0, 5 2, 5 Port 1, 5, 6, 22, 34, 35, 65, 66 Port 3, 5, 8, 22, 66 Port 6, 5 Port 8, 5 Power on, 4, 21 Prescaler, 14, 16, 17 Priority, 10 Pull-up resistor, 5, 8, 12, 36 Pull-up resistor, 12, 37 Pulse-length meter, 14 Push-pull outputs, 5 PWM, 14, 17
E
EMU, 4, 12, 21 Event counter, 14
F
Frequency counter, 14
G
Generator, 4, 5, 14
H
Handshake, 12
I
I/O lines, 4, 5 I/O page, 5 IM bus interface, 4, 12, 13, 36 Internal time reference, 14 MICRONAS INTERMETALL
R
R/W mode, 8 R/W-line, 5, 34, 65 RAM, internal, 4 Rate multiplier, 14 59
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
RESET, 5, 8, 10, 11, 13, 17, 21, 22, 22, 31, 66 ROM, 4 RTI, 10
T
Timer, 14 Timers, 4, 14, 17, 22, 66
S
Serial interface, 14 Slave registers, 12, 13 Speed, 12 Stand-by option, 4 Start and stop detector, 14
W
Watchdog, 4, 19, 22, 66
X
X1, 34 X2, 34 XTAL1, 5 XTAL2, 5
60
MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
6. Addendum: CCU 3000, CCU 3000-I EMU Versions The CCU 3000 TCs 10, 12, 16, 1, and CCU 3000-I TCs 1 and 3 are emulator versions (EMUs). They differ from production versions in the programmability of control register bit 5: If this bit is set to 0, the CCU assumes to have a clock signal at its X1-pin instead of a crystal connected at pins X1 and X2. X2, in that case, works as a clock output delivering the inverted processor 2 output signal. 2-switch fosc 2 4 3
Fig. 6-1: X1, X2 Position shown: 2-switch = 1 XTAL-mode
0201H Bit 7 6 5 4 3 2 1 0
Control Register Reset copy from addr. FFF9H PHI2-out: `0' = active, `1' = inactive external bus: `1' = bus on ports 0, 1, 2 disabled R/W signal / Port4: `0' = R/W, `1' = P40 internal ROM: `1' = internal ROM enabled internal RAM: `1' = internal RAM enabled internal CPU: `1' = internal CPU enabled x Read x Write no function - set to `1' (to keep compatibility) no function - set to `1' (to keep compatibility) PHI2-out: `0' = active, `1' = inactive Bus disable: `1' = disable bus on ports 0, 1, 2 R/W signal / Port4: `0' = R/W, `1' = P40 ROM enable: `1' = enable internal ROM RAM enable: `1' = enable internal RAM CPU enable: `1' = enable internal CPU
MICRONAS INTERMETALL
61
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
7. Addendum: CCU 3000 1 m Version As the 1 m version of the CCU has faster pin signal drivers than the 1.2 m version, it may be programmed to work in a kind of "slow mode", i.e.: the current of the pin driver transistors in that mode is limited to 35 to 40%. In this default mode it is compatible with the 1.2 m version. 020EH Bit 7 to 3 2 1 0 Fast/Slow Register Reset x 0 0 0 Read x x x x Write x Port 6: 0 = slow, 1 = fast Ports 5, 7, 8, Timers 1, 2, 3, IR, IM bus: 0 = slow, 1 = fast Ports 1, 2, 3, 4,: 0 = slow, 1 = fast
7.1. Electrical Characteristics 7.1.1. Absolute Maximum Ratings
Symbol Voltages VDD VI Currents IDD ISTBY II IO IO Temperatures TA Ts Power Pmax Power Dissipation - 1210 800 mW mW TA 70 C, 68-pin PLCC , TA 70 C, 64-pin SDIP Ambient Temperature under Bias Storage Temperature - -10 80 C C Supply Current Standby Current Input Current Output Current Output Current 1 5 7 to 68 7 to 60 61 to 68 -50 -280 -2 -5 80 50 2 5 30 mA mA mA mA mA (except Port 6) (Port 6 only) Supply Voltage Input Voltage on any pin 1 1 to 68 -0.5 -0.3 6.5 VDD+0.3 V V Parameter Pin No. Min. Max. Unit Test Conditions
-
-40
125
Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
62
MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
7.1.2. Recommended Operating Conditions at VDD = 4.75 V, TAMB = 0 C to 70C
Symbol Input Voltages VINL VIH Input Low Voltage Input High Voltage 3, 4 3 4, 6-68 Vss - 0.3 2.8 - - 0.8 VDD +0.3 V V Parameter Pin No. Min. Typ. Max. Unit Test Conditions
Open Drain Output Voltages VOH Output High Voltage 61-68 - VDD +0.3 V (Port 6 only)
Standby Voltage VSTBY Clock Input FXTAL 4 0.5 - 8 MHz external clock 5 3 - 5.25 V
Capacitive Load on Address, RWQ and Data Pads (Port1, Port2, Port3, Port4) CADF 17-41 CADS 100 pF Bus slow mode t020Eu, Bit0=1 30 pF Bus fast mode t020Eu, Bit0=0
7.1.3. Recommended Crystal Characteristics at CXTAL1 = CXTAL2 = 22 pF1p; Cstray 2 pF
Symbol Parameter Pin No. Min. Typ. Max. Unit Test Conditions
Quartz (XTAL1/XTAL2) fp R1 C0 C1 P fp / fH Parallel Resonance Frequency Series Resistance - - - - 4-8 - - 40 150 7.0 20 - - MHz pF fF mW dB CL= 13 pF 8 MHz 4 MHz
Shunt Capacitance Motional Capacitance Rated Drive Level Spurious Frequency Attenuation
- - - -
- - - 20
- - 0.02 -
MICRONAS INTERMETALL
63
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
7.1.4. DC Characteristics at VDD = 4.75V to 5.25V, TAMB = 0 C to 70C,fXTAL = 8 MHz, for 68-Pin PLCC Package
Symbol IDD Parameter Supply Current (no external load, CMOS-levels on inputs) Standby Current Power-On Reset Voltage Pin No. 1 Min. - Typ. 8/16 Max. 15/30 Unit mA Comment @ 4/8 MHz
ISTBY VPOR
5 6 4 4.2
1 4.75
A V
VDD=0V, VSTBY =5V
Inputs (all inputs except XTAL1) VILH VIHL (VILH-VIHL) ILI Schmitt Input L H Transition Voltage Schmitt Input H L Transition Voltage Schmitt Input Hysteresis Leakage Current 3, 6-68 0.38 VDD 0.20 VDD 0.10 VDD -1 2.15 0.56 VDD 0.29 VDD 0.27 VDD 1 V
3, 6-68
1.15
V
V A Vss VIN VDD
Outputs (push-pull or push-pull/open-drain switch: P1..5, P7..8, T1..3, IR, XTAL2) VOL VOH Output Low Voltage Output High Voltage 17-60 VDD - 0.4 0.4 V V IOUT=4mA IOUT=-4mA
Outputs (open-drain with weak pull-up: IMB_ID1, IMB_DAT1, IMB_CL1, IMB_ID2, IMB_DAT2, IMB_CL2, RESQ) VOL VOH IOHS Output Low Voltage Output High Voltage Output High Short Circuit Current 17-60 VDD - 0.4 -50 0.4 V V A IOUT = 4 mA IOUT = -2 A VOUT = VSS Output data = 1
Outputs (open drain, with clamping diode: P6) VOL Output Low Voltage 61-68 0.5 V IOUT= 25 mA
64
MICRONAS INTERMETALL
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
7.1.5. AC Characteristics at TAMB = 0 C to 70C, VDD = 4.75 V to 5.25 V, Cl = 0 pF External Loads: add 0.75 ns/pF for controller output lines Symbol tcyc tPWL tAH tADS tDSR tMDS tDHW tDHR tRWH tWRH tP5S tX1PH2 tPH2X2 Parameter Cycle Time Pulse Width Low Address Hold Time Address Setup Time Data Setup Time Read Write Data Delay Write Data Hold Time Read Data Hold Time Read/Write Hold Time Read/Write Hold Time Delay Port1 to Port3 Select Lines Delay X1 to internal 2 Internal 2 to X2 Output 17 17 42-47 4 3 18-25 Pin 3 3 26-41 Min. 125 60 10 15 20 10 9 10 10 13 12 7 5 24 34 26 15 10 29 16 Max. 2000 1000 22 34 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
MICRONAS INTERMETALL
65
3000-I, CCU3001-I CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
8. Addendum: CCU 3000-I Specification 8.1. Changes to CCU3000 Instead of the Master/Slave IM bus Interface IM1 of CCU3000, an I2C/IM bus Master is used. Source 3 of the interrupt controller is not connected. Its priority has to be set to `0'. Source 4 of the interrupt controller is connected with Port81 (Special Input). Falling edges of port 8, bit 1 generate interrupts if the priority of this interrupt source is not set to 0. In I2C mode it is possible to switch I2C_CLK from IM1_CLK_Pad to IM1_ID_Pad. Therefore two I2C busses can be driven (see section 8.6. for details). The CCU 3000-I is available in two different packages, see pages 71 to 73. All other features are the same as in CCU3000. 8.2. Definitions 8.3. Interrupt Definitions Interrupt 0 1 2 3 4 5 6 7 RESET Source TIMER1 TIMER2 TIMER3 NC P81 IM-BUS2, Master IM-BUS2, Slave P87 Vector (low, high byte) FFF6, FFF7 FFF4, FFF5 FFF2, FFF3 FFF0, FFF1 FFEE, FFEF FFEC, FFED FFEA, FFEB FFE8, FFE9 FFFC, FFFD 22CH 22DH 22EH 22FH 230H 232H 233H 234H 235H 236H 237H 238H 239H 23AH 23CH 23DH 23EH 23FH 240H 241H 242H 243H 244H 245H 246H 247H 249H 24AH 24BH 24CH 24EH Timer 2 control byte 1 Timer 2 control byte 2 Timer 2 control byte 3 Timer 2 prescaler low byte Timer 2 prescaler high byte Timer 2 accu low byte Timer 2 accu high byte Timer 2 adder low byte Timer 2 adder high byte Timer 3 control byte 1 Timer 3 control byte 2 Timer 3 control byte 3 Timer 3 prescaler low byte Timer 3 prescaler high byte Timer 3 accu low byte Timer 3 accu high byte Timer 3 adder low byte Timer 3 adder high byte Port 6 Data Direction Register Port 6 Port 7 Data Direction Register Port 7 Port 8 Data Direction Register Port 8 IM-Bus 2 control & status IM-Bus 2 transfer rate IM-Bus 2 master address IM-Bus 2 master data low IM-bus 2 master data high IM-bus 2 slave 1, IM address 02 IM-bus 2 slave 2, IM address 03 MICRONAS INTERMETALL 205H 206H 207H 208H 209H 20AH 20BH 20CH 20DH 20FH 21CH 21DH 21EH 21FH 220H 221H 222H 223H 224H 225H 226H 228H 229H 22AH 22BH Port 2 Data Direction Register Port 2 Port 3 Data Direction Register Port 3 Port 4 Data Port 5 Mode Register Port 5 Direction Register Port 5 Data IR-Input Port 7 Mode Register Interrupt controller control byte Interrupt controller return byte Interrupt controller priorities source 0 & 1 Interrupt controller priorities source 2 & 3 Interrupt controller priorities source 4 & 5 Interrupt controller priorities source 6 & 7 Timer 1 control byte 1 Timer 1 control byte 2 Timer 1 control byte 3 Timer 1 prescaler low byte Timer 1 prescaler high byte Timer 1 accu low byte Timer 1 accu high byte Timer 1 adder low byte Timer 1 adder high byte
8.4. Memory Mappings RAM ROM Control byte I/O 0000H to 01FFH 0300H to 063FH 8000H to FFFFH FFF9 0200 to 02FF Page 0, 1 Page 3, 4, 5, 6 (CCU3001-I only)
8.5. I/O Definitions Address 200H 201H 202H 203H 204H 66 Function Clock frequency Control register Watchdog Port 1 Data Direction Register Port 1
CCU 3000-I, CCU3001-I CCU 3000-I, CCU 3000-I CCU 3000, CCU 3001-I CCU 3001, CCU 3001-I
250H 2D0H 2D1H 2D2H 2D3H 2D4H 2D5H 2D6H 2D7H 2D8H 2D9H 2DAH 2DBH 2E0H to 2E7H 2FEH 2FFH IM-bus 2 slave 3, IM address 04 I2C Start Cycle without generation of ACK (ACK = `1') I2C Start Cycle with generation of ACK (ACK = `0') I2C Resume Cycle without generation of ACK (ACK = `1') I2C Resume Cycle with generation of ACK (ACK = `0') I2C Termination Cycle without generation of ACK (ACK = `1') I2C Termination Cycle with generation of ACK (ACK = `0') I2C / IM bus Data from Receive-FIFO I2C / IM bus Status IM bus Start Cycle IM bus Resume Cycle IM bus Termination Cycle I2C / IM bus Prescaler External addresses, used for EMU boards Reserved, do not use Reserved for testing purposes where n is the value of bits 0 to 6 and the setting value (0 = reset state means n = 128). A complete telegram is assembled by the software out of individual sections. Each section contains an 8-bit data. This data is written into one of the nine possible Control-Data registers. Depending on the chosen address, a certain part of an I2C or IM bus cycle is generated. By means of corresponding calling sequences it is therefore possible to join even very long telegrams (e.g. long data files for auto increment addressing of I2C slaves). The software interface contains a 3 byte deep FIFO for the control-data registers as well as for the received data. Thus all IM and most of the I2C telegrams can be transmitted to the hardware without the software having to wait for empty space in the FIFO. All address and data fields appearing on the bus are constantly read and written into the Read-FIFO. The software can then check these data in comparison with the scheduled data. If a read instruction is handled, the interface must set the data word FFH so that the responding slave can insert its data. In this case the ReadFIFO contains the read-in data. If telegrams longer than 3 bytes are received, (1 address, 2 data bytes), the software must check the filling condition of the control data FIFO and, if necessary, fill it up (or read out the Read-FIFO). A variety of status flags is available for this purpose: - The `half-full' flag is set if there are more than two bytes available in the Transmit-FIFO. - Bus Busy is activated by writing any byte to any one of the data transfer registers. It stays active until the I2C or IM bus activities are stopped after the stop condition generation. So `Busy' becomes inactive after the data that was written in one of the four registers to terminate the bus action is completely shifted out, and the bus-specific stop condition is generated (see Fig. 2-22, 2-25). Moreover, in the I2C mode the ACK-bit is recorded separately on the bus lines for the address and the data fields; however, the interface itself can set the address ACK=0. In any case the two ACK flags show the actual bus condition. These flags remain until the next I2C start condition is generated.
8.6. I2C and IM Bus Interface The master bus interface can generate two different kinds of format: - I2C format - IM format The MSBit of the bus prescaler registers (address 2DBH) is used to switch I2C_CLK between IM1_CLK_Pad and IM1_ID_Pad. The remaining 7 bits can be used to set the bit rate. bit 7 bit 6 to 0 0 = I2C_CLK at IM1_ID_Pad, 1 = I2C_CLK at IM1_CLK_Pad (reset state) bit rate fIMI2C = fOSC / (4 * n) for n>1
MICRONAS INTERMETALL
67
CCU 3000, CCU 3000-I 3000-I, CCU 3001-I 3000-I CCU 3001, CCU 3001-I
Table 2-1: I2C and IM bus interface registers For example, the software has to work off the following sequence (ACK =1) to read a 16-bit word from an I2C device address 10H (on condition that the bus is not active):
Address
2D0H(w)
Function
generate I2C start condition, transfer Data as I2C address, and set ACK=1 same as above, ACK=0 output 8 I2C Data bits, set ACK=1 same as above, set ACK=0 output 8 I2C Data bits, set ACK=1, generate I2C stop condition same as above, set ACK=0 receive FIFO status flags: bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 not used 1= receive FIFO empty 1= contr-dataFIFO half full 1= Bus busy I2C I2C data ACK adr ACK
2D1H(w) 2D2H(w) 2D3H(w) 2D4H(w)
-write 21H to 2D0H -write 0FFH to 2D2H -write 0FFH to 2D4H -read dev. address2D6H -read 1. databyte 2D6H -read 2. databyte 2D6H
check receive FIFO empty flag (bit 1, 2D7H) before read
2D5H(w) 2D6H(r) 2D7H(r)
The value 21H in the first step results from the device address in the 7 MSBs and the R/W-bit (read=1) in the LSB. If the telegrams are longer, the software has to ensure that neither the Control-Data-FIFO nor the Read-FIFO can overflow.
To write data to this device: -write 20H to -write 1. databyte to -write 2. databyte to
2D0H 2D2H 2D4H
"OR"ed ACK not used
The bus activity starts immediately after the first write to the Control-Data-FIFO. In the I2C mode the transmission can be synchronized by an artificial extension of the Low phase of the clock line. Transmission is not continued until the state of the clock line is High once again. Thus a slave (software slaves!) can adjust the transmission rate to its own abilities.
2D8H(w) 2D9H(w) 2DAH(w) 2DBH(w)
generate IM-address field generate 8 IM-data bits generate 8 IM-data bits and the IM-stop condition terminal select & speed
The I 2C/IM bus interface is a pure Master system, Multimaster busses are not realizable. The ident, clock and data terminal pins have open-drain outputs with weak pull-up transistors.
68
MICRONAS INTERMETALL
CCU 3000-I, CCU 3001-I CCU 3000-I, CCU 3000-I CCU 3000, CCU 3001-I CCU 3001, CCU 3001-I
UNIT = Bit-Period
1 SD SCL 1 2 1 1 4
Ident Data Clock 1 4 1 4 1 4
Fig. 2-20: Start condition I2C bus
Fig. 2-23: IM bus start condition
Ident SD repeated 7 times SCL 1 4 1 2 1 4 Clock 1 4 1 4 1 4 1 4 Data
Ident 1 on the 8th address bit only
clock stays high on the last data bit before stop
Fig. 2-21: Single bit on I2C bus
Fig. 2-24: Single bit on IM bus
Ident SD SCL 1 4 3 4 Data Clock 1 4 1 2 1 2
Fig. 2-22: Stop condition I2C bus
Fig. 2-25: Stop condition IM bus
MICRONAS INTERMETALL
69
3000-I, CCU 3001-I CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
WR_Data (chosen address = control info)
D0 to D7 WR
Address Decoder
Transmit FIFO 3 x 11 Control Data Clock Ident
in
SR
out
Transmit Logic
Receive FIFO 3x8 empty
Receive Logic
Start Condition resets ACK flags SR SR Q
half full
D0 to D7 Dat or ADR ACK ready
Q
DAT_ACK
ADR_ACK
D0 to D7 Fig. 2-26: I2C/IM bus interface
RD_Status (2D7H)
70
MICRONAS INTERMETALL
CCU 3000-I, CCU 3000-I 3001-I CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
8.7. Pin Connections and Short Descriptions DA ID = IM bus data line of external devices = IM bus ident line of external devices Pin No.
68-pin PLCC 64-pin SDIP
CL SDA SCL X
= IM bus clock line of external devices = I2C bus data line of external devices = I2C bus clock line of external devices = obligatory; connections depend on application Short Description
Connection
I: Input O: Output
Pin Name
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
16 15 14 13 12 11 10 9 8 - - - 7 6 5 4
+5V GND Xtal Xtal +3V +5V X DA/SDA ID/SCL CL/SCL DA ID CL X X X external infrared receiver X X X X X X to
I I I/O I I I/O I/O O O I/O O O I/O I/O I/O I
VSUP GND X2 X1 Vstandby RES IM1_DAT/I2C_DAT IM1_ID/I2C_CLK2 IM1_CLK/I2C_CLK1 IM2_DAT IM2_ID IM2_CLK TIMER1 TIMER2 TIMER3 IR
Supply Voltage Ground Crystal Connector 2 Crystal Connector 1 Standby Supply Voltage Reset input / Reset output IM bus 1 Data line/ I2C Bus Data line IM bus 1 Ident line/ I2C Bus Clock line IM bus 1 Clock line/ I2C Bus Clock line IM bus 2 Data line IM bus 2 Ident line IM bus 2 Clock line Timer 1 input/output Timer 2 input/output Timer 3 input/output Infrared Signal Input
17 18 19 20 21 22
3 2 1 64 63 62
I/O (O) I/O (I/O) I/O (I/O) I/O (I/O) I/O (I/O) I/O (I/O)
P4 (R/W) P10 (D0) P11 (D1) P12 (D2) P13 (D3) P14 (D4)
Port 4, Bit 0 (CPU read/write) Port 1, Bit 0 (CPU data bus bit 0) Port 1, Bit 1 (CPU data bus bit 1) Port 1, Bit 2 (CPU data bus bit 2) Port 1, Bit 3 (CPU data bus bit 3) Port 1, Bit 4 (CPU data bus bit 4)
MICRONAS INTERMETALL
71
3000-I, CCU 3001-I CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
Pin No.
68-pin PLCC 64-pin SDIP
Connection
I: Input O: Output
Pin Name
Short Description
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
X X X X X X X X X X X X X X X X X X X X X X X X X X X X
I/O (I/O) I/O (I/O) I/O (I/O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O (O)
P15 (D5) P16 (D6) P17 (D7) P20 (A0) P21 (A1) P22 (A2) P23 (A3) P24 (A4) P25 (A5) P26 (A6) P27 (A7) P30 (A8) P31 (A9) P32 (A10) P33 (A11) P34 (A12) P35 (A13) P36 (A14) P37 (A15) P50 (RD Port 1) P51 (WR Port 1) P52 (RD Port 2) P53 (WR Port 2) P54 (RD Port 3) P55 (WR Port 3) P70 (Memory Bank Address 0) P71 (Memory Bank Address 1) P72 (Memory Bank Address 2)
Port 1, Bit 5 (CPU data bus bit 5) Port 1, Bit 6 (CPU data bus bit 6) Port 1, Bit 7 (CPU data bus bit 7) Port 2, Bit 0 (CPU address bit 0) Port 2, Bit 1 (CPU address bit 1) Port 2, Bit 2 (CPU address bit 2) Port 2, Bit 3 (CPU address bit 3) Port 2, Bit 4 (CPU address bit 4) Port 2, Bit 5 (CPU address bit 5) Port 2, Bit 6 (CPU address bit 6) Port 2, Bit 7 (CPU address bit 7) Port 3, Bit 0 (CPU address bit 8) Port 3, Bit 1 (CPU address bit 9) Port 3, Bit 2 (CPU address bit 10) Port 3, Bit 3 (CPU address bit 11) Port 3, Bit 4 (CPU address bit 12) Port 3, Bit 5 (CPU address bit 13) Port 3, Bit 6 (CPU address bit 14) Port 3, Bit 7 (CPU address bit 15) Port 5, Bit 0 (CCU read Port 1) Port 5, Bit 1 (CCU write Port 1) Port 5, Bit 2 (CCU read Port 2) Port 5, Bit 3 (CCU write Port 2) Port 5, Bit 4 (CCU read Port 3) Port 5, Bit 5 (CCU write Port 3) Port 7, Bit 0 (Memory Bank Address 0) Port 7, Bit 1 (Memory Bank Address 1) Port 7, Bit 2 (Memory Bank Address 2)
72
MICRONAS INTERMETALL
CCU 3000-I, CCU 3000-I 3001-I CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
Pin No.
68-pin PLCC 64-pin SDIP
Connection
I: Input O: Output
Pin Name
Short Description
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
33 32 31 30 29 28 27 26 - 25 24 23 22 21 20 19 18 17
X X X X X X X X X X X X X X X X X X
I/O (O) I/O (O) I/O (O) I/O (O) I/O (O) I/O I/O /I I/O I/O I/O /I I/O I/O I/O I/O I/O I/O I/O I/O
P73 (Memory Bank Address 3) P74 (Memory Bank Address 4) P75 (Memory Bank Address 5) P76 (R/W) P77 (Power-Down Control) P80 P81/INT P82 P83 P87/INT P60 P61 P62 P63 P64 P65 P66 P67
Port 7, Bit 3 (Memory Bank Address 3) Port 7, Bit 4 (Memory Bank Address 4) Port 7, Bit 5 (Memory Bank Address 5) Port 7, Bit 6 (CPU read/write signal) Port 7, Bit 7 (Power-Down Control) Port 8, Bit 0 Port 8, Bit 1 / Interrupt input Port 8, Bit 2 Port 8, Bit 3 Port 8, Bit 7/Interrupt input Port 6, Bit 0 Port 6, Bit 1 Port 6, Bit 2 Port 6, Bit 3 Port 6, Bit 4 Port 6, Bit 5 Port 6, Bit 6 Port 6, Bit 7
8.7.1. DC Parameters I2C Bus Master Interface The input and output parameters of the I2C bus interface (Clock and Data) are designed according to the INTERMETALL specification for Port and IM bus pins (the interface can also be operated as IM bus interface). The differences are: Symbol UIL UIH UOL Meaning Input Low Voltage Input High Voltage Output Low Voltage INTERMETALL max. 1 V min. 2.8 V 0.4 V / 2 mA I2C Specification max. 1.5 V min. 3 V 0.4 V / 3 mA
The INTERMETALL parameters are equivalent to software I2C bus solutions using Port-lines for the bus. In applications with series resistors in the clock or data line these differences may become important. MICRONAS INTERMETALL 73
CCU 3000, CCU 3000-I 3000-I, CCU 3001-I 3000-I CCU 3001, CCU 3001-I
8.8. List of Registers that Differ from CCU 3000, CCU 3001 The IM1 Registers of CCU3000 (Addr. from 0210H to 021BH) are no longer available. 02D0H Bit 7 to 0 I2C Start Cycle without Generation of ACK (ACK = 1) Reset x Read x Write I2C-Start-Data
02D1H Bit 7 to 0
I2C Start Cycle with Generation of ACK (ACK=0) Reset x Read x Write I2C-Start-Data
02D2H Bit 7 to 0
I2C Resume Cycle without Generation of ACK (ACK = 1) Reset x Read x Write I2C-Resume-Data (set this byte to $FF for a read access)
02D3H Bit 7 to 0
I2C Resume Cycle with Generation of ACK (ACK=0) Reset x Read x Write I2C-Resume-Data (set this byte to $FF for a read access)
02D4H Bit 7 to 0
I2C Termination Cycle without Generation of ACK (ACK =1) Reset x Read x Write I2C-Terminate-Data (set this byte to $FF for a read access)
02D5H Bit 7 to 0
I2C Termination Cycle with Generation of ACK (ACK=0) Reset x Read x Write I2C-Terminate-Data (set this byte to $FF for a read access)
02D6H Bit 7 to 0
I2C/IM Bus Data from Receive-FIFO Reset x Read Received data Write x
74
MICRONAS INTERMETALL
CCU 3000-I, CCU 3000-I CCU 3000, CCU 3001-I CCU 3001, CCU 3001-I
02D7H Bit 7 6 5 4 3 2 1 0 I2C/IM Bus Status Reset 0 0 0 0 0 0 0 0 Read x I2C I2C I2C OR'D ACK ADDR-ACK Data-ACK Write x x x x x x x x
Bus busy WR FIFO half full RD FIFO empty x
02D8H Bit 7 to 0
IM Bus Start Cycle Reset x Read x Write IM bus start-(address)-data
02D9H Bit 7 to 0
IM Bus Resume Cycle Reset x Read x Write IM bus resume data
02DAH Bit 7 to 0
IM Bus Termination Cycle Reset x Read x Write IM bus terminal data
02DBH Bit 7 6 to 0
I2C/IM Bus Prescaler Reset 1 0 Read x x Write select I2C_CLK2 on IM1_ID / select I2C_CLK1 on IM1_CLK fIMI2C = fOSC / (4*n) for n>1 fIMI2C = fOSC / 6 for n=1 fIMI2C not running for n=0
MICRONAS INTERMETALL
75
CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I
9. Data Sheet History 1. Data Sheet "CCU 3000, CCU 3000-I, CCU 3001, CCU 3001-I", Feb. 14, 1995, 6251-367-1DS: First release of the data sheet.
MICRONAS INTERMETALL GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@intermetall.de Internet: http://www.intermetall.de Printed in Germany by Simon Druck GmbH & Co., Freiburg (02/95) Order No. 6251-367-1DS
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery dates are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, MICRONAS INTERMETALL GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Reprinting is generally permitted, indicating the source. However, our prior consent must be obtained in all cases.
76
MICRONAS INTERMETALL
End of Data Sheet
Multimedia ICs
MICRONAS
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